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Optimizing DSP processing power through glueless PCI bus transmission

Posted: 03 May 2000 ?? ?Print Version ?Bookmark and Share

Keywords:texas instruments? ti? iic taipei 2000? dsp? pci bridge?

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60 International IC ? Taipei ? Conference Proceedings Optimizing DSP processing power through glueless PCI bus transmission Parman Lee Texas Instruments Abstract As DSP applications continue their rapid proliferation, many applications, such as data acquisition, test and measurement, industrial controls and other data processing functions, now use multiple DSPs to offload certain processing responsibilities from the general-purpose central processing unit (CPU). This frees the host CPU to perform the administrative duties it is best suited for while the high-speed processing capabilities of DSPs are applied to intense data processing tasks. This has led to the need for a high-speed, high-bandwidth data transmission solu- tion to connect the multiple DSPs to the PCI bus to take advan- tage of the DSP's real-time processing power. Solutions include implementing a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or using a PCI- to-DSP bridge to provide a glueless connection between the host port interface (HPI) port on the DSP to the high perfor- mance PCI bus. This paper will assert that the PCI-to-DSP bridge provides the ideal glueless transmission path between the PCI local bus and a DSP subsystem, simplifying the system designer & rsquo;s task and bringing DSP designs to market faster. The first part describes the fundamentals of the PCI bus, its future and opera- tions. The second part describes the DSP host port interface (HPI) and the purpose of the PCI-to-DSP bridge. In the last part, an example of the glueless interface between a DSP sub- system and the PCI local bus is illustrated. Introduction Many traditional analog functions in electronic equipment have been digitized with ADC and DSP embedded. The in- creasing demand on the information-flow performance for the applications between computer and communication (C&C) also tells that some high-speed data transmission media is required. However, in the past and even till now, the industry is somehow used to an 8-bits or 16-bits legacy host bus with operating fre- quency far below 33Mhz. While the computing power of DSP keep innovated dramatically, it is necessary for the industry to find some alternative way to remove the transmission bottle- neck on low-speed host bus for DSP applications and the sys- tem operations. PCI bus, as being the most popular and mature Peripheral Component Interconnect bus for years in computer industry, has become the next candidate of today with adequate bandwidth for the industrial applications in bank of DSPs to capture, process, and transmit information under the control of a host CPU. PCI Local Bus and Extensions The PCI local bus was developed with 32-bits and 64-bits synchronous transaction and typical operating clock frequency at 33Mhz or up to 66Mhz. The bus can be processor indepen- dent although it uses little endian notation. The configuration space of each PCI device on the bus is memory-mapped which bring a host system with PCI bus to be re-configured in plug- and-play style without hard-wired jumper or DIP switch set- ting. User can easily add a new PCI device into a PCI system with least intervention. The maximum throughput of a 32-bits 33Mhz PCI bus can be 132Mbyte per second at continual burst mode. The bandwidth doubled when data width or bus fre- quency doubled. The bus supports master mode so that mul- tiple agents with optional locking mechanism for atomic op- eration on the bus is possible. The maximum number of PCI device on a bus is 256. PCI-to-PCI Bus Extension The PCI bus architecture allows bus expansion by a PCI-to- PCI bridge. The primary PCI bus is the one that locate closer to Host CPU, where the secondary PCI bus is the far one. PCI bus 0 is defined as the closest PCI bus to Host CPU. The maximum number of such bus hierarchy can be up to 256 as well. It also allows PCI-to-Expansion Bus through an expan- sion bus bridge, such as PCI-to-ISA bridge, PCI-to- HPI bridge, etc. Peer-to-peer bus access as well as access to main memory and devices on the expansion bus or another PCI bus are sup- ported. Detail protocols can be found in PCI-to-PCI bridge spec.. Compact PCI and Hot Swap Extension Compact PCI has emerged as an important and necessary standard for industrial computers and embedded systems. With the Eurocard packaging standard, it's the plateform ideal for International IC ? Taipei ? Conference Proceedings 61 telecommunication, data communications, and other industries. Compact PCI is electrically identical to PCI local bus. Additionally, it supports the latest processors while supporting a variety of operating systems and software. The flexibility allows sys- tem designers to leverage it to various applications with specific needs. Since it is critical for tele- communication and embedded systems to upgrade, configure or replace damaged adapter card without shutting down the system, the PCI Hot Swap speci- fication was developed to provide the ability to in- sert or remove an adapter card from an operational system without interfering with other PCI devices on the bus. Mini PCI and PCI-X Extension Mini PCI is another form factor definition for communica- tion peripherals such as modems and NICs, and target at small and mobile systems. PCI-X is an intended spec. to extend PCI bus spec. by defining a new standard designed to address the I/ O bottleneck at the high-end PC/server level. It defines a 64- bit bus with clock speed of 133Mhz. Gagabit Ethernet and Fiber Channel can be the appropriate applications for PCI-X bus extension so far. Bus Connection between DSP and Host CPU As mentioned earlier, PCI bus is the most popular host bus architecture with high-speed and high-bandwidth advantages as well as bus-expansion capability. Then, what about the bus interface with DSP in terms of PCI bus with host CPU? Un- like general-purpose processor at host, the DSP architecture can vary with different digital signal processing functions and ap- plications, such as fixed point and floating point capability can be the two major categories in the industry. However, with the most popular DSP in the marketplace, HPI, Host Port Inter- face, becomes the most familiar parallel bus by DSP designers in the industry. It's a port interface for a host device or host processor to interact with DSP. The information is exchanged between host device and DSP memory through dedicated ad- dress and data registers. Both host device and DSP control the operation and communicate the status through a control regis- ter. The data transfer rate on HPI can be ranging from 64Mbit per second up to 160Mbps for single DSP process. Next, the host device described here may not be a PCI de- vice and there is actually no connection between HPI and PCI. Then, how to connect DSP HPI to PCI local bus for the best system performance as many DSP designers want to utilize comprehensive features and resources around PCI local bus? Fortunately, with the PCI flexible bus architecture, the PCI-to- Expansion Bus concept is applicable for a PCI-to-HPI bridging design. With PCI rich bandwidth, the bridge should be ca- pable to optimize multiple DSP operations within a system. An Example to Optimize DSP Processing Power with PCI Bus This example is a PC-based audio stereo application with DSP at the expansion bus from a PCI bridge device. At right is the system block diagram to explain this application concept. As shown, the audio stereo codec provides sample rates from 8Khz to 96Khz. The DSP in this system is to process audio data then send the data processed to PC system by a PCI-DSP bridge, i.e. a bridge between HPI and PCI bus. The PCI bus here is not necessary to PCI local bus. It can be Compact PCI bus with hot swap feature. References ? PCI Local Bus Specification 2.2, PCI Special Interest Group, Portland OR, 1998 ? PCI Bus Power Management Interface Specification Rev. 1.1, PCI Special Interest Group, Portland OR, 1998 ? Compact PCI Hot Swap Specification, PICMG 2.1, Rev 1.0 ? Mini PCI Specification, Rev. 1.0 Review Draft,Aug. 13,1999 ? Advanced Configuration and Power Interface Specification Rev. 1.0 ? PCI System Architecture, Tom Shanley and Don Anderson, Addison Wesley, 1995 ? PCI2040 PCI-DSP Bridge Controller Data Manual, Texas Instruments, July 1999 ? TMS320C5410 Data Sheets, Texas Instruments, June 1999 Author's contact details Parman Lee Texas Instruments 25F, 216 Tun Hwa S. Road, Section 2, Taipei, Taiwan Phone: 886 2 2376 2835 E-mail: rhl@ti.com 62 International IC ? Taipei ? Conference Proceedings Presentation Materials International IC ? Taipei ? Conference Proceedings 63 64 International IC ? Taipei ? Conference Proceedings International IC ? Taipei ? Conference Proceedings 65 66 International IC ? Taipei ? Conference Proceedings International IC ? Taipei ? Conference Proceedings 67 68 International IC ? Taipei ? Conference Proceedings




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