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FPGAs/PLDs??

24-bit magnitude comparator with 50ns response

Posted: 01 Sep 2000 ?? ?Print Version ?Bookmark and Share

Keywords:atmel? fpga? pga? gate array? programmable logic?

This application note demonstrates how to implement the AT6000 Series FPGA as a magnitude comparator that can compare two 24-bit binary integers in 50ns.

View the PDF document for more information.



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