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Deep signal and design integrity assured in SoCs

Posted: 01 Dec 2000 ?? ?Print Version ?Bookmark and Share

Keywords:aggressor net? signal integrity? electromigration? hot electron? self heat?

These days, there is a lot of noise about signal integrity and design integrity in deep-submicron SoC designs. And there is a good reason: Shrinking processes and higher frequencies mean even second-order physical effects can create problems. Designers cannot achieve timing closure, or may have their chips fail on the tester, because signal-integrity effects created logic and timing problems.

Crosstalk-induced errors are the most common signal-integrity problems. They are induced when two or more nets (wire routes) run parallel to one another for some distance, creating a capacitor between them. This capacitor can transmit a pulse from one net to another. If an "aggressor" net switches, this may cause the adjoining "victim" net to temporarily assume a different logic value, resulting in unintended logic transitions. The outcome is repeatable failures of certain logic operations.

Even if a signal has the correct logic value, crosstalk can affect the timing of transitions. This can cause failure to perform at speed, even when the chip is new. Timing dependence on crosstalk is a subtle and complex matter because the timing on victim nets depends on the delay across the first gate, interconnect delay and the behavior of other adjacent nets. Instead of a single delay value for interconnect, we now have minimum and maximum delays, which can vary from one cycle to the next. This additional delay variation can preclude timing closure.

A third signal-integrity problem is voltage drop on power supply lines. On every chip, a network of wires distributes power from the pads to the circuitry inside. Since these wires have resistance, the voltage that gets to the internal circuitry is less than that applied to the chip. If this voltage drop, often called IR drop, is too severe, the circuits will not get enough voltage, resulting in malfunction or timing failure.

Design integrity problems

Three common design integrity problems that occur in the field are electro-migration, hot electron degradation and wire self-heat. Electro-migration occurs when the dc current density in a power supply line is too high, causing the wire's metal grains to be pushed aside by the constant electron wind.


The hot-electron or short-channel effect results from high electric fields between the source and drain of a device, causing electrons to speed up in the channel. The fastest electrons damage the oxide and interface near the drain, and the transistor threshold and mobility change over the life of the part. Since most transistors always have the same applied polarity, the shift adds up as the device continues to run. Eventually, the threshold shifts so far the device no longer meets specifications.

Wire self-heat, sometimes called signal line electro-migration, is a mechanical failure in the wire caused by frequently varying thermal conditions. As pulses go through the wire, the power dissipated by the wire causes it to heat above oxide temperature. The difference in the thermal constants between the oxide and the wire causes mechanical stress and the wire may eventually fail.

These problems have always existed, but at 0.25?m and below, an intelligent design solution must be adopted or chips will fail. Traditional approaches analyze after design-signal and design-integrity analyses are conducted after layout and extraction. These tools can identify problems, but offer no automated fixes or guidance to the designer on how to resolve them. In deep-submicron design, crosstalk analysis and parasitic extraction are no longer post-layout tasks; they must be performed concurrently with design. The tools should also be flexible, since the amount of effort expended on signal integrity will depend on the application?a few transient errors and a short chip life may not be a big problem for a video game, but could mean life or death for the wearer of a pacemaker.

We have reached an inflection point in technology innovation where post-layout signal and design integrity analyses no longer suffice. Some new solutions promote signal integrity awareness to all the phases of the design cycle, from physically knowledgeable synthesis to detailed routing. The most effective solution is holistic and gives a broad perspective of signal integrity, timing, power and area concerns as the designer navigates different tools. In cases where prevention is impractical, the tools determine automated ways of correcting signal integrity problems without disturbing other design parameters.

The severity of many problems, including crosstalk, can be reduced by using a placement tool enhanced with signal integrity and design-integrity features. During initial placement, net adjacencies, layer assignments and exact routing topologies are unknown. An advanced placer uses driver strength, estimated routing and signal RCs to estimate signal slews and identify potential victim nets. The placer then decides to shorten the affected wires, use a stronger driver or insert buffers to break long wires into shorter segments. This decision is based on full knowledge of design constraints and accurate prediction of downstream technologies.

Also during concurrent placement and optimization, the placer detects wire self-heat problems by analyzing net length, and estimating wire RCs, signal slews and maximum operating frequencies. Average, peak and RMS currents are compared with ac current density limits for layers, and the results analyzed to determine the best solutions. Increasing wire width is an obvious way to fix a current-density problem, but if the current is caused by the capacitance of the wire itself, increasing its width may not solve the problem. Alternatives include decreasing the length of the wire, driving smaller gates and inserting buffers so one driver need not drive the entire problematic net.

As with wire self-heat, hot-electron problems are detected through analysis during placement and concurrent optimization. Each gate has a damage per transition computed from input slope and output load, which determines the potential total damage. The placer compares this with the maximum allowable damage for each gate, and if the damage limit is exceeded the placer decides how best to fix the problem.

Crosstalk-induced timing shifts cannot be eliminated by any practical technique short of shielding all nets, which doubles the routing resource requirements. However, increasing timing margins to account for the extra delay can control the problem. This approach has been used for many years in the guise of multiplying the cross-coupling capacitances by a constant greater than one to account for the Miller effect. However, instead of this global overestimate, a more detailed analysis can correctly account for the timing shift on each net, resulting in a less pessimistic timing analysis. If the timing shift for a given net is excessive, it can be minimized by employing post-routing optimization techniques, such as using extra spacing for nets, and can be virtually eliminated by using shielding. Since both those solutions are costly in terms of routing resources, they are used only for critical nets such as clocks.

? Lou Scheffer

Member, SP&R Group

Cadence Design Systems Inc.





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