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Single-mask simplicity needed for SoC

Posted: 01 Jun 2001 ?? ?Print Version ?Bookmark and Share

Keywords:soc? rtos? smp? fpga? pld?

The move to multimillion-gate chips has made it necessary to adopt design-reuse strategies for new SoC devices. An increasing number of metal layers eliminated traditional gate array technology as a viable option and shrinking mask lithography increased the nonrecurring-engineering costs above $500,000 per prototype.

A low-cost, high-performance product is needed in a marketplace where the cost of going to silicon is heading upward of $1 million.

A technology that employs single-metal-mask programmable interconnects is a viable alternative that can deliver an efficient solution. The interconnect programming provides a low-NRE option for configuration, with performance closer to standard cell and turnaround time closer to FPGA. The single-mask programming technology can be used for standalone ASIC products as well as for IP cores designed for implementing within a SoC platform-based design.

However, even with a single-mask programming (SMP) solution to implement an embedded design, designing millions of gates is unacceptable from a cost and time-to-market perspective. Hence the need for kernels. A kernel is defined as a customizable hard core that contains the common IP used for all the derivative designs in a specific marketplace. This kernel consists of the application programming interface, RTOS, processors, bus, memory and critical common I/O functions. These are optimized for performance, size or power as required by the market segment for which the platform is designed.

Creating a platform SoC, which consists of a kernel and an SMP fabric that can be customized for each derivative, would further reduce the NRE and manufacturing turnaround time over their proposed standard-cell implementation.

A number of SMP architectures exist in the marketplace. All of them have a pre-existing structure of wire segments, connected by jumpers patterned on the customized metal layers. Those wire segments connect small structures of transistors or simple gates into custom user logic.

The technology worked well with two or three layers of interconnect, but becomes via-constrained as technology moves toward six to eight metal layers?contacts to these small device and gate structures need to traverse all the way to upper metal layers, creating large vertical blockages and congestion on the custom layers.

On the other hand, FPGA designers have long recognized that it would take fewer interconnects to wire larger-granularity cells together. Fewer interconnects imply fewer jumpers to connect them and coarse-grained cells also require proportionally less jumper customization at top metal layers. Consequently, the silicon area can be more efficiently used.

eCell designs

Based on these observations, a novel fabric has been designed that combines the advantages of large FPGA-like SRAM-programmable logic cells?called eCells?that are connected by segmented pure-metal routing, using SMP. The proposed structure has FPGA-like programmability with density and performance closer to standard cells due to its metal interconnection.

The eCell consists of a pair of three-input lookup tables (LUTs), connected to a flip-flop through a MUX. A two-input NAND gate drives one input of each LUT. It also includes two inverters of different strength, which can be separately connected to any signal to re-drive it.

The complete cell, equivalent to about 12 logic gates, needs only three metal jumpers for configuration. With conventional metal, this is a two-customized mask process: one via and one wire mask. With the more recent mechanical planarization and copper-metal process, the vias and metal are patterned from one mask. A standard via mask is used in conjunction with the customized metal mask.

The basic cell is tiled in a 16-by-16 array (or eUnit), with no routing channels between the cells. Eight such units make up the basic configurable embedded core, or eCore. Each eCore has its own built-in scan string.

Specific signals can easily be assigned connection locations for subsequent wiring when configuring the core. The actual number of I/O connections is in the thousands, but varies depending on the number of inter-connect layers available.

By fine-tuning the devices inside the eCell coupled with selectable output drive, the resulting power and performance numbers are much closer to standard cells than FPGAs.

Platform design

Such an SMP fabric can be used within a platform design to accelerate the design turnaround time even further. In general, all the variations that may occur in a derivative design should be targeted to be outside the hardened part of the kernel. This should include the interrupt controller, timers or counters, protocol for the memory controller, USB stack and all interface logic.

The skinny platform has the advantage of using an existing SMP fabric chip, thereby minimizing the platform design costs. Furthermore, the user obtains the entire fixed-platform IP with a single purchase and therefore avoids the hassle of costly and lengthy IP acquisition.

? Laurence H. Cooke, Zeev Wurman

eASIC Corp.





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