Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Verification tool enables rapid ASIC prototyping

Posted: 11 Mar 2002 ?? ?Print Version ?Bookmark and Share

Keywords:mentor graphics? formal verification tool? fpga tool? asic prototyping? soc prototyping?

Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification (DSV) environment from Mentor Graphics Corp. addresses all hardware prototype creation and verification challenges, from partitioning, debug and interconnect to rapid board creation and analysis.

Claimed to provide in-circuit verification that is three to four times faster than low-end tools, the verification system test silicon prototypes at speeds comparable to a real-time operating environment, thereby reducing silicon respins.

"For advanced flows making use of high-end emulation tools, SpeedGate DSV can be used to create low cost ASIC replicates that can be passed to software engineers for rapid system debug. For cost-constrained methodologies, SpeedGate DSV delivers close to at-speed system verification at orders of magnitude faster than low-end solutions," adds Anne Sanquini, VP and GM of Mentor Graphic's HDL Design Division.

The verification system employs a partitioning approach for logic and I/O among multiple FPGAs that addresses both I/O distribution and emulation prototype speed issues. It solves the granularity problem by creating an intermediate level of granularity at the process level while maintaining the RTL database. The processes are "encapsulated" into individual entities that can move anywhere in the hierarchy and reduce the number of FPGAs required in the prototype ASIC.

For designs that can't have the number of I/Os go beyond the pin-count of the FPGA, the system adds logic to the FPGA to make an I/O pin perform the function of multiple pins. An I/O Management tool provides a wrapper feature that automatically creates logic to allow specific pins to handle multiple signals as defined by the user.

The SpeedGate DSV also allows designers to import ASIC RTL into the system and view files either as block diagrams or interconnect tables. Design information can then be exported for partitioning, formal verification and synthesis, simplifying overall design management.

The system also features source control features, including check-in/checkout commands that help designers to manage multiple versions, as well as track any changes, to the source code.

The verification system supports all fixed-routed, reconfigurable, multiple, and custom PCBs. It runs on the Solaris 2.7 and 2.8 OS, and extends support for ASIC partitioning on Xilinx's Virtex FPGAs.

The SpeedGate DSV is priced at $98,500 for a floating license.





Article Comments - Verification tool enables rapid ASIC...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top