Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

DFT confronts test cost in design run

Posted: 16 Apr 2002 ?? ?Print Version ?Bookmark and Share

Keywords:bist? dft? soc? control logic? scan technique?

This technical article offers a synopsis of the challenges in SoC design, particularly with regard to test costs.

View the PDF document for more information.



Article Comments - DFT confronts test cost in design ru...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top