Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

ChipPAC designs five-stacked chips in 1.4mm package

Posted: 07 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:memory chips? CSP? Flash chips? SRAM? PSRAM?

ChipPAC Inc., a provider of semiconductor assembly and test services, has engineered five-stacked memory chips in a 1.4mm thick package. The CSP includes two Flash chips, SRAM, PSRAM and spacer chip. ChipPAC designed and simulated the total package's electrical, thermal and mechanical reliability using its proprietary SmartDESIGN process.

Stacked chip packaging is suitable for applications where high memory capacity in a compact footprint can be met by stacking different memory chips into a single package that is the size of a typical one chip CSP. Similarly, a DSP or an ASIC is assembled with a controller and stacked memory to produce higher functionality at higher speed without increasing the footprint size.

"Our latest five-stacked CSP doubles the memory capacity of the 1.4 mm thick three-stacked package introduced just last year, while providing broad design flexibility and dramatically saving customers on packaging costs. We are already in development with a six-stacked CSP in the same profile with 75?m thick die," Marcos Karnezos, CTO for ChipPAC said.





Article Comments - ChipPAC designs five-stacked chips i...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top