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Papers reveal Synopsys, Cadence research projects

Posted: 28 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:EDA software? Synopsys? formal verification? Design Automation Conference? FPGA?

Innovation is alive and well at the two largest EDA software suppliers, with Synopsys Inc. moving ahead in formal verification, test and synthesis, and Cadence Design Systems Inc. breaking new ground in timing analysis, asynchronous design and model reduction, according to technical research papers presented at the 39th Design Automation Conference (DAC) earlier this month.

As is common with research papers, it's not known when, or whether, the described technologies will become part of a commercial EDA offering.

One Synopsys paper showed some new thinking in the application of combinational equivalency checkers to sequential designs. It described a heuristic algorithm that uses automatic test pattern generation for matching "compare points" based on the functionality of combination blocks in sequential designs. The authors claimed that experiments on seven industrial circuits proved the method on designs of up to hundreds of thousands of gates.

In another paper, Synopsys authors described four new Boolean satisfiability (SAT) optimization techniques: partial clauses, back-leaps, immediate implications and local decisions. SAT solvers are widely used in formal equivalency checkers and property checkers. The authors claimed the new techniques outperform existing methods by 1.5 to 60 times.

An author from Synopsys' Advanced Technology Group contributed to a paper on symbolic simulation. It discussed special constructs that require unique treatment in symbolic simulation, such as arrays, and presented an array model for symbolic simulation that handles those constructs for regular structures such as FPGAs and memories.

Four Synopsys authors presented a new approach to logic built-in self-test. They proposed an "interval-based scan-unload method" that is said to resolve the fault-diagnostic challenges typically attributed to BIST. The method is said to provide diagnosis resolution down to gate-level faults, with minimal hardware overhead.

Delay-fault testing

Synopsys authors contributed to another paper that outlined a new method for enhancing delay-fault testing by using multiple clock frequencies. It suggested that using a carefully selected clock, combined with a second set of ac delay patterns, can enhance the overall quality of tests.

A Synopsys co-author contributed to a paper that suggested a new algorithm for memory allocation and assignment in high-level synthesis. The approach promises to expand the range of possible, and practical, memory configurations. Another Synopsys researcher co-authored a paper on task scheduling and voltage selection for power minimization. It outlined a two-phase approach to help designers execute tasks at low voltage levels, across a range of system configurations.

One Synopsys paper described an efficient routing database that's claimed to handle designs with up to 370 nets flat using an interval-based approach. But the paper was written before Synopsys acquired Avanti Corp.'s Milkyway database.

Two Synopsys papers were of a more tutorial nature. One described the interface logic models and extended timing models used by the PrimeTime timing analyzer, with experimental results. In another, Synopsys teamed up with 0-In Design Automation Inc. and Broadcom Corp. to describe an RTL C-based design methodology.

Cadence authors, meanwhile, presented a new approach to timing models that's said to provide up to twofold capacity improvements. The approach generates a gray-box timing model from a gate-level netlist by reducing a timing graph. It is claimed to support arbitrary levels of latch-time borrowing as well as timing constraints that span multiple blocks.

Cadence teamed up with design services firm Reshape Inc. to present a design flow for asynchronous circuits that is based entirely on commercial EDA tools. It generates null convention logic circuits that are faster than equivalent synchronous circuits but consume more area.

In a paper that won one of several DAC 2002 "best paper" awards, a Cadence co-author helped present a new approach to model order reduction for physical verification tools. A new family of algorithms promises to compute passive, reduced-order models of controllable accuracy for state-space systems with arbitrary internal structures. Another Cadence paper presented new research in time-domain RF analysis, suggesting a hybrid "frequency time" approach that can handle distributed RF components in steady-state, time-dependent simulations.

Other EDA vendors that contributed to DAC technical papers included Lisatek; Mentor Graphics; Prover Technology; Silicon Perspective, which was recently acquired by Cadence; and Virage Logic. Portions of the DAC proceedings are available online.

? Richard Goering

EE Times





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