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MaxCore tool, processor, MaxSim developer suite

Posted: 13 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:TeakLite? DSP core? 2G? 2.5G? wireless communication?

DSP Group presents simulation model for 16-bit core

DSP Group Inc. has launched the simulation model for its TeakLite DSP, a 16-bit core targeted for applications such as 2G and 2.5G wireless communication, as well as Internet audio formats, including MP3 and WMA, and Voice-over-IP phones.

The model was developed using AXYS Design Automation Inc.'s MaxCore tool and the processor description in C-based Language for Instruction Set Architectures (LISA). The MaxCore model delivers over one million cycles per second on a 1GHz Pentium host and supports scalable multicore simulation and debugging. The company's set of hardware test vectors has been applied to verify the functional match between the simulation model and its RTL reference on a cycle-by-cycle basis.

The model of the TeakLite DSP core is part of the MaxLib library of processor models for AXYS' MaxSim Developer Suite. According to AXYS, with the MaxSim, users can create complete, application-specific platform models with multiple cores as virtual prototypes for early architecture exploration, pre-silicon embedded software development, and multicore debugging.





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