Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Chip alliance rolls in 90nm CMOS platform

Posted: 30 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS design platform? CMOS technology?

Motorola Inc., Royal Philips Electronics, and STMicroelectronics have jointly developed a 90nm CMOS design platform. Earlier this year, the three companies formed an alliance to develop future generation CMOS technology, from the 90nm node down to 32nm over the next five years.

The new 90nm CMOS design platform, available from all three companies, takes full advantage of the multiple features and modularity of 90nm process technology. The multiple threshold-based library elements can be selected at the design level and used in the same design block, providing platform users greater flexibility to optimize performance and power consumption. This capability is expected to enable faster development of chips for power-sensitive applications.

The design platform is fully supported by CAD tools from Cadence, Mentor Graphics, and Synopsys through design solutions that are developed in partnership with their individual R&D groups.





Article Comments - Chip alliance rolls in 90nm CMOS pla...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top