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IP TripTik needed on SoC highway

Posted: 18 Nov 2002 ?? ?Print Version ?Bookmark and Share

Keywords:ip? intellectual property? design reuse? soc design? 90nm?

By this fall, hundreds of SoC design teams around the world will be targeting 90nm process technologies. Though schedules vary, the leading foundries and integrated device manufacturers expect to make system-chips on 90nm design rules by next spring.

With transistor counts of 100 million or more translating into gate counts of 20 million plus, these SoC devices will - with few exceptions - include IP brought in from a company's own IP repository or purchased from a commercial IP vendor. Dabs of memory placed here and there, DSPs and microcontrollers, USB and other interface circuitry . . . the list is long.

To broaden their IP offerings and to develop a new revenue stream, companies such as IBM, Motorola, Philips, STMicroelectronics, and many others are forming partnerships with two ideas in mind. One thrust is to create process platforms that include a core digital transistor that will be as close to or the same as possible among the various partners. The other prong is to create both hard and soft IP that can be easily swapped among the partners and sold to other vendors.

Consider Motorola, which recently announced that it will co-develop process technology with two European partners, STMicroelectronics and Philips, at a 300mm development fab at Crolles, France. These companies have been "aligning" their processes with TSMC.

At the 90nm node and beyond, the trio will be able to provide one another with IP from within their own repositories and from commercial IP vendors qualified on TSMC's processes, said Craig Lage, a director at Motorola's semiconductor process R&D center.

IBM is taking a similar track. The company wants to develop IP libraries that can be sold to companies that would have the option of fabbing their SoC designs at a foundry.

Will it work? Or will these designs get bogged down in legal tangles, in which the secret sauce within an IP block is patented-protected from deep disclosure to a design team at one of the partners or commercial IP providers? Will the design team have the same understanding as the team that originated the IP of what "functional verification" means? Contributors to the week's In Focus section consider the steps SoC design teams can take to ensure that verified IP blocks will work properly in the context of a full chip.

- David Lammers

EE Times





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