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IDT ships zero delay buffers, programmable skew devices

Posted: 12 Dec 2002 ?? ?Print Version ?Bookmark and Share

Keywords:integrated devices technology? teraclock? zero delay buffer? programmable skew device?

Integrated Device Technology Inc. has introduced the TeraClock family of zero delay buffers and programmable skew devices that support the high-speed I/O standards required in next-generation communications applications, such as network routers, wireless 3G basestations, and SANs.

The family also offer what the company claims to be the industry's broadest range of translation capabilities between I/O standards with five user-configurable single-ended or differential signal variants at the input and four signal variants at the output, as well as pin-to-pin compatibility for ease of migration between the zero delay buffer and programmable skew devices.

The TeraClock devices provide reliable signals through its PLL capabilities, and capitalize on its redundant clock and hitless switchover feature to maintain and ensure overall system integrity and reliability in the event of a disruption in the system's main clock signal.

The devices operate at frequencies up to 250MHz and offers 50ps cycle-to-cycle jitter and 100ps output to output skew. The TeraClock products are available in single-ended 2.5V TTL, 1.8V LVTTL; differential 2.5V LVTTL, 1.8V LVTTL, HSTL, eHSTL and LVPECL; and pseudo-differential 2.5V TTL, 1.8V TTL, HSTL, eHSTL and LVPECL input signals, and HSTL, eHSTL or 1.8V/2.5V LVTTL outputs in various combinations.





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