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SystemC seen accelerating simulation

Posted: 28 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:systemc? simulation? dvcon design and verification conference? verification library? software development platform?

SystemC is seeing increasing use as a way of accelerating simulation, according to speakers at the DVCon Design and Verification Conference. Meanwhile, speakers noted important milestones coming up in 2003 for the Open SystemC Initiative's (OSCI) standardization efforts.

"There are people out there using SystemC right now," said Stan Krolikoski, OSCI chairman. "It will be used with other languages, but it has a place of its own." Krolikoski said SystemC is being used at three levels: at an "untimed" level for pure functional modeling, a transaction level, and the RTL.

Kevin Kranen, OSCI president, noted that the group completed a SystemC 2.0 Language Reference Manual (LRM) in December, which is still under review. This coming April, he said, OSCI expects to complete a SystemC 2.1 LRM, and that version will go to the IEEE for standardization. Also expected in April is SystemC Verification Library 1.0, the first production version of SystemC's testbench generation capability.

In 2003 and 2004, Kranen said, OSCI will be working on a synthesizable subset of SystemC, standards for transaction-level modeling, and enhancements for software modeling. He described OSCI as an "open source oriented organization" that's looking for contributions from the engineering community.

Mike Baird, president of Willamette HDL, described how and why SystemC is actually being used. The primary reason, he said, is to speed simulation performance. He said about half of users are employing SystemC as a software development platform, and the other half are using it for system-level modeling, particularly performance analysis.

Some users are starting at the untimed level, but most are starting with SystemC's transaction-level modeling, Baird said. Most users then translate to HDLs for hardware implementation, although a few, particularly in Japan, are trying SystemC as a "single language" solution all the way through the design flow, he noted.

One audience member asked whether SystemVerilog, which includes C-like modeling features, will steal some of the thunder from SystemC. "We're trying to avoid language wars," said Krolikoski. "There's a different user base for the two languages, although some users will have to make decisions as to which one to use."

- Richard Goering

EE Times





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