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Ready for the Verilog split?

Posted: 02 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:system verilog 3.1? ieee 1364 standard? verilog? cadence? synopsys?

Warning of possible industry "havoc," Cadence Design Systems has sounded the alarm about possible incompatibility between System Verilog 3.1 and IEEE 1364 standard Verilog.

Cadence's motives are certainly subject to question, but the concern should not be ignored.

In an EDA Views column that appeared recently on EEdesign.com, Mitch Weaver, vice president of marketing for systems verification at Cadence, warned of the possibility that Verilog could split into two languages. "This could spell disaster for all involved," he said.

Weaver said there is no discussion about how to integrate SystemVerilog with IEEE 1364 Verilog, that many proposed SystemVerilog extensions are in "direct conflict" with IEEE 1364 Verilog and that some of the proposed SystemVerilog additions were previously rejected by the IEEE.

In a responding EDA Views column, consultant Stu Sutherland - who serves on both the Accellera SystemVerilog committee and the IEEE 1364 group - argued otherwise. Sutherland said there is a strong working relationship between Accellera and IEEE, that full compatibility with IEEE 1364 Verilog is a "strong consideration" for all SystemVerilog enhancements and that prior "rejection" of a language feature does not mean it should not be considered now.

Some observers see Cadence's stance as a marketing ploy, or as part of the perpetual Cadence vs. Synopsys battle. Synopsys, which donated much of the technology behind SystemVerilog 3.1, is probably well ahead of Cadence in implementation.

And yet, Cadence has a point. The SystemVerilog 3.1 language reference manual that Accellera will soon release is not an IEEE standard. Consultant Cliff Cummings, who like Sutherland serves on both the Accellera and IEEE committees, said that the user-oriented IEEE may well see things differently from the EDA-vendor-dominated Accellera.

Cadence will not serve its users by trying to hold back what will almost certainly be the next generation of Verilog. And Synopsys will not serve its users by pushing out early SystemVerilog 3.1 tools.

Meanwhile, as Cummings has noted, nobody fully and consistently implements Verilog 1364-2001. Maybe that is a good place to start.

- Richard Goering

EE Times





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