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New FPGAs revolutionize system design

Posted: 02 Jun 2003 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? asic? logic chip? gate array? programmable logic?

Faced with the daunting challenge to bring new products to market faster, designers are seeking affordable and flexible alternatives to high-cost custom chips. Traditional ASICs and gate-array solutions no longer cut it in a world where mask charges have skyrocketed to over $1 million per spin.

In today's uncertain economy, programmable chips are emerging as the product of choice for many applications due to their inherent flexibility, performance, functionality, and competitive pricing. FPGAs are becoming the optimal choice for today's higher volume designs.

One of the main differences between a traditional logic device and an ASIC is the term "system-on-a-chip," which historically has been reserved just for ASICs. That position has changed radically now that intellectual property (IP) immersion processes are so successful for embedding system-component IP into FPGAs.

New platform FPGAs

Some FPGA vendors are now making soft and hard microprocessors available, so users can craft the solution best suited for their embedded applications. Partnering with industry leaders in the microprocessor arena provides mature processor hard cores in a variety of high-performance configurations. You can choose devices that include hard-IP processors and can utilize the on-chip memory to guarantee a fixed latency of execution for higher determinism.

Innovative FPGA suppliers have also introduced 32-bit soft microprocessor cores that can stand alone or complement hard-core processor applications. You can add soft-core computing applications to your platform FPGA designs or, using the same bus standard, introduce soft microengines to offload time-consuming functions from the main hard-core processor. Soft-core processors do not have the same performance of hard-core types, but they are small and limited only by the size of the FPGA. By supporting both hard and soft-core processors, an engineering team can create the ideal platform for its specific application.

Peripherals and other system IPs are ideally soft in these programmable platforms, so you can choose exactly what you want "running out" of that IP. Gone were the days of placing additional microprocessor packages on a board - not to use the processor cores themselves, but to supply the required amount of discrete hard IP.

FPGA providers should supply a standard library of IPs, including cores like arbiters, bridges and UARTs. An additional desired feature is the support necessary for customizing IP to such a detailed level that designers can trade off features, performance and size of every piece of IP.

DSP functionality is exploding in these new FPGA systems in the form of hardwired multipliers that yield billions of MAC/s support. This capability greatly exceeds even the fastest of sequential DSPs available in the market today. The sweet spot for FPGAs in DSP applications is in the 1MSa/s to 300MSa/s region, where customers are most concerned with high performance and flexibility.

Another key advantage of this new breed of platform FPGAs is flexible connectivity. These FPGAs have to interface to a wide range of products to provide a complete design platform. HSTL and SSTL allow efficient memory interfaces, while LVDS provides a high-speed link that avoids crosstalk and other interference. Platform FPGAs offer support for I/O standards and designers can use soft IP building blocks for a wide range of interface protocols such as PCI 32/33 and PCI 64/33, RapidI/O, POS PHY Level 4, Flexbus 4, SPI-4, and HyperTransport.

However, the challenge in developing a low-cost FPGA is to develop a small die to save costs, yet have enough I/O pads around the periphery of the smaller die to offer adequate I/O. Logic chip designers have found a solution with staggered pad technology that implements two rings of I/O pads around the periphery of the die to maintain I/O counts with ever-decreasing die size.

- Rob Schreck

Sr. Marketing Manager

Xilinx Inc.





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