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Design challenges and sign-off criteria in nanometer era

Posted: 16 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:nanometer sign-off? ir drop? electromigration? 3d parasitic extraction? crosstalk?

At 130nm and below, chip manufacturing is facing various signal integrity related failures. These are due to reduced feature sizes, decrease in wire pitch, lower power supply voltages and shrinking threshold voltages. From 180nm down to 130nm, wires are being packed more closely together. As a result, the fraction of total wire capacitance represented by lateral coupling increases dramatically.

This is responsible for a dramatic increase in on-chip crosstalk noise. Another key factor that contributes to electrical problems in nanometer designs is increased clock frequencies with faster on-chip slew rates. Faster slew rates create more switching noise and increase instantaneous power consumption. This, in turn, puts stress on the power grid, resulting in voltage (IR) drop and electromigration.

Nanometer sign-off is the final verification to assure that a design does not have electrical issues that will result in chip failure after manufacture. However, finding problems just before tapeout could lead to multiple design iterations and missed schedules. Therefore, nanometer sign-off is best applied as part of a thorough design closure methodology that addresses issues such as signal and power integrity from early chip planning to tapeout.

The final sign-off phase should be more thorough than the design closure tools. Sign-off tools must also be silicon-proven. The full-chip examination should include analysis of the subtle and complex interactions that occur between many different electrical effects. For example, nanometer sign-off should predict how IR drop affects crosstalk and how this influences timing, which in turn affects power responsible for IR drop. The key components of nanometer sign-off include accurate 3D parasitic extraction, full-chip IR drop analysis, full-chip crosstalk analysis and SI-aware static timing analysis (STA) that accounts for the influence of both crosstalk and IR drop.

3D parasitic extraction

In nanometer processes, wire delay is the primary contributor to overall system delay. Cross-coupling between wires is responsible for crosstalk noise that can cause timing and functional problems. Accurate parasitic extraction on resistance and capacitance between wires is the first essential step in performing nanometer sign-off.

The best way to extract parasitic capacitance or resistance is to use a 3D field solver. However, 3D field solvers do not have the capacity or performance required to analyze all nets on a complex chip. These tools would require literally weeks to extract the parasitics of a nanometer-scale design. In contrast, advanced 3D parasitic extraction tools that use analytical formula are capable of performing detailed, full-chip parasitic extraction in a matter of hours.

By using pre-characterized coefficients created from either field solver or silicon measurements, these analytical extractors can achieve accuracy within 5 percent of field solver results. Since the specifications that describe these complex process variations must be supplied by or derived in cooperation with silicon foundries, foundry support is essential to accurate full-chip extraction. Each new process generation creates new challenges, and the tools and extraction files can be kept current only through close work with foundry partners.

IR drop on a power grid occurs when parasitic effects, such as resistance or capacitance, cause a decrease in the current flowing through the power grid from the Vdd (source) I/O pins, or bump bonds in the case of flip-chips to the transistors or gates of a design. If a device does not receive the required voltage through the power grid, its performance may be compromised, leading to design timing problems and functional failures.

Typically, a 5 percent drop in supply voltage can affect delay by 15 percent or more. Such an increase in delay is critical when clock skews are in the range of 100ps. IR drop can also make path delay unpredictable and can even cause a change in the critical path of a design. Hence, nanometer timing calculations must take IR drop into account.

A complete picture of power grid integrity can only be obtained when effects such as IR drop, ground bounce and electromigration are computed and analyzed accurately. Many power grid verification tools rely on oversimplifications such as black-boxing embedded IP blocks or using simple power-consumption distribution models, thus trading accuracy for speed. However, because the current flowing through a chip's power grid does not stop at the ports of cells and IP blocks, power grid verification tools must be accurate to the transistor level while maintaining the speed and efficiency required for large-scale nanometer designs. The ability to pre-characterize the power grids of library elements facilitates the reuse strategies that are central to nanometer design styles.

Crosstalk analysis

Crosstalk analysis considers the effect of wire coupling on the performance and functionality of a design. The primary source of wire coupling is wire-to-wire capacitances, though, for very high-speed nanometer designs, inductive coupling can also be a problem.

Functional errors due to crosstalk are caused by transient glitches that are strong enough to cause a temporary logic change to appear on otherwise static signals. A glitch could raise a true functional impact when it propagates to a storage element such as flip-flop or latch. Consequently, to verify whether crosstalk would induce functional problems, it is not sufficient just to determine if a signal is subject to a sizeable noise pulse. The circuit must be tested to determine if that noise pulse will reach a storage element. Therefore, effective sign-off crosstalk analysis must include accurate noise glitch calculation and noise propagation.

Accurate noise glitch calculation must account for temporal and logical relationships of the aggressor signals, as well as the holding resistance of the victim driver. When a driver is holding a static logic state, its resistance is larger than when it is switching. Therefore, noise calculations using switching resistance derived from standard timing libraries over-estimate noise. A separate cell library characterization step is required to calculate holding resistance.

For accurate noise propagation, simulation of the receiver input noise is required to determine the amount of noise to propagate. Since digital CMOS logic gates are inherently noise-immune and act as low-pass filters, most glitches will be filtered before they are latched. Without accurate noise propagation, the number of functional failures will be greatly exaggerated, while at the same time, the true crosstalk-induced functional errors could easily be overlooked.

Crosstalk can either increase or decrease signal timing delay; it all depends on whether the victim net and aggressor net are switching in same direction. If victim and aggressor signals are transitioning in the same direction, the victim-signal delay increases. In addition, this "camel's hump" or non-monotonic waveform at victim signal affects the slew rate as well. Consequently, crosstalk effects on delay and slew can percolate through a circuit, dramatically altering its timing characteristics.

To accurately calculate crosstalk effects on delay, special calculation techniques are required to deal with the volume of parasitic data, the non-monotonic waveform shapes that occur when aggressor signals switch, and the complex timing and logic relationships between aggressors and victims. The delay for each victim net is calculated with all of the aggressor nets switching simultaneously in the opposite direction for maximum delay, or in the same direction for minimum delay as the victim net.

SI-aware STA

An SI-related chip problem can be raised by many different noise sources, such as crosstalk and IR drop. Therefore, it must have an SI-aware delay calculation that can comprehend the interaction of various noise sources. In sign-off flow following 3D parasitic extraction, IR drop analysis is performed to determine the worst-case IR drop for each cell instance. This information is then used as input to SI-aware STA and crosstalk-glitch analysis.

Unlike traditional static-timing sign-off, SI-aware timing sign-off accurately calculates delays in the presence of noise (both crosstalk and IR drop), resolves the interdependency between crosstalk and timing data (arrival times and slews), and avoids overly pessimistic approximations. SI-aware timing analysis must also filter unrealistic combinations of SI events, either automatically or via user control. A timing sign-off flow that blindly uses worst-case data and accumulates all SI delay effects will likely render an unattainable timing target. Finally, the SI-aware sign-off timing analysis must be supported with the library data necessary to permit accurate calculation of SI effects.

- Daniel Siu

Regional Technical Marketing Manager, ICD, Asia Pacific Operations

Cadence Design Systems Inc.





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