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Engineer creates HDL generation language

Posted: 23 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:programming language? confluence? launchbird design systems?

A declarative, functional programming language that eases RTL code generation is now going into beta sites, and is available for free downloading from the creator's web site. The language, Confluence, is the creation of Tom Hawkins, former FPGA designer and now president of Launchbird Design Systems.

While there are already a plethora of design languages available, Hawkins feels he has something unique. Confluence, he says, provides a simple and clean way to describe extremely complex systems in just a few lines of code, with much more flexibility than today's HDLs. Confluence is then compiled into VHDL, Verilog, Phython, or C.

Rather than an HDL itself, Confluence is a "generator language" whose programs are algorithms that produce RTL structures. "A Confluence program generates an entire class of circuits, whereas an HDL will only focus on the specific circuit you have in mind," Hawkins said. "An HDL has some configuration parameters, but the constructs in Confluence are much more flexible."

As an example, he noted, Confluence can describe a finite impulse response (FIR) filter in just a few lines of code, yet allow reconfiguration of inputs and coefficients. "DSP systems work really well in Confluence because of the symmetry of DSP structures," he said.

Confluence is a synchronous RTL language that supports parallelism, hierarchy, and dataflow. It offers such programming features as recursion, lexical scoping, higher-order data types, and referential transparency. Hawkins said that many of the language's features are unavailable in VHDL or Verilog.

Hawkins said that Confluence grew out of work he did for an FPGA design services firm, where he developed a tool that could move VHDL designs into Python. However, Confluence isn't specific to FPGAs and can also be used for ASIC design, he noted.

Launchbird Systems offers a Confluence compiler that generates Verilog, VHDL, Python, or C. Hawkins has added tools to automatically generate assertion monitors. The first license of the compiler is available for free, with additional seats at $240 per month. An online compiler at the Confluence web site lets users enter trial programs.

Examples of Confluence-generated Verilog, VHDL, C, and Python are available at the OpenCores web site.

- Richard Goering

EE Times





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