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Toshiba develops nine-layered packaging technology

Posted: 23 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:Toshiba? ic packaging? nand? flash memory?

Toshiba Corp. said it has developed a multichip package that can stack up to nine chips in its 1.4mm high package. The technology adds three additional layers to the same height currently used for six-layer packages. Toshiba expects new technology will provide more powerful and functional solutions in a single package.

The new package combines a range of memory chips, including SRAM, SDRAM, pseudo-SRAM, NOR flash memory and NAND flash memory.

The nine-layer package uses Toshiba's technology to grind each chip to a thickness of 70?m. Then it can be stacked without breakage, said a Toshiba spokesman. The chip is 15?m thinner than conventionally used chips in multichip packages, he said.

A sample showing a common combination of chips houses SRAM, SDRAM, three NOR flash and one NAND flash with three spacers. Total capacity for the device was 776 Mbits. The sample measures 11-by-14mm and is 1.4mm high. It uses 225 balls with a 0.65mm pitch. Power supply was 1.8 V.

The package provides Toshiba's proprietary three-bus system for data transfer between the multichip package and a CPU. A high-speed bus supports SDRAM and NOR, a middle-speed bus supports SRAM and NOR and a dedicated bus supports NAND.

Toshiba will begin volume production of the multichip package that include memory combinations specified by customers.

- Yoshiko Hara

EE Times





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