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Startup to speed co-verification

Posted: 05 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:hardware? software co-verification? adveda? univers? simulator?

A small EDA startup based in Eindhoven, Netherlands, has big plans to speed up hardware/software co-verification. The company, AdvEDA B.V., will preview its Univers line of hardware/software co-verification tools at the Design Automation and Test in Europe conference in Paris this month.

The company was founded when Cor Schepens, a former Adelante executive, brought together Huub Erens, who was developing a fast instruction-set simulator (ISS) and debug technology, and Mark Seutter, who was developing a fast cycle-based simulator.

The three men pitched the idea of combining the technologies to Henk Aerts, who provided cash to launch the company.

AdvEDA has done more than integrate Erens' and Seutter's tools, said Schepens, who is AdvEDA's CEO. It has ensured that the cycle-based simulator and ISS run off the same simulation kernel.

This removes one of the major bottlenecks in hardware/software co-verification, Schepens said. The hardware engine of co-verification tools typically uses one kernel, the software engine uses another and the translator between them a third kernel that unnecessarily slows down performance, he said.

AdvEDA uses one simulation kernel in its flagship tool, named Marvelous Integrated System Simulation, or "Miss Univers," Schepens said. This approach is much faster than other co-verification tools, cutting days off setup and simulation time, and simplifying testbench creation, he said.

Hardware simulators have typically been the slowest piece and, therefore, have limited hardware/software co-verification environments, Schepens said, but Miss Univers uses a speedier cycle-based simulator that has been benchmarked as 100x faster than leading VHDL event-driven simulators.

"Because we have a cycle-based simulator, the overall simulation speed is much better," he said. "And with Miss Univers, you don't lose any speed changing from one protocol to another protocol and from one tool to the other."

The instruction-set simulators are built with AdvEDA's proprietary technology, and provide cycle-accurate ISS of more than 1 million cycles per second, Schepens said. Close integration unifies debugging between hardware and software, he said.

Users can see registers from an ISS in the waveform view mixed with hardware signals, Schepens said. Conversely, they can select registers in the hardware and display them within the register view of a chosen processor.

The tool's integrated development environment contains editors for both embedded software and RTL source code. The hardware tool and the software tools can also be licensed separately, the company said.

The standalone cycle-based simulator, named the Marvelous RTL Simulator, or "Mrs. Univers," supports RTL VHDL at present, and Verilog support is planned for future releases, Schepens said. It is faster than other cycle-based simulators and incorporates intuitive features not found in most other implementations, he said. For example, the tool can handle the full RTL VHDL synthesizable syntax, including multiple asynchronous clocks, tristate signals and undefined values when reading memory or external signals.

Meanwhile, AdvEDA is also licensing in a standalone configuration the Marvelous Advanced Debugger and Model environment, or "Madam Univers."

Miss Univers' pricing starts at $25,000 and Mrs. Universe's starts at $10,000. AdvEDA doesn't yet have a price for Madam Univers.

Schepens said the five-member company plans to double its staff in the coming months. Erens is CFO, Seutter is chief architect of hardware tools and Aerts is CTO at the company.

Chief executive officer Cor Schepens discusses AdvEDA's perspective on hardware/software co-verification in an EDA Views column at EEdesign.com.

- Mike Santarini

EE Times





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