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Zarlink PLLs ensure reliable data transport

Posted: 12 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:zarlink semiconductor? pll? zl30100? zl30101?

Zarlink Semiconductor Inc. has disclosed that its two new digital PLLs deliver industry-leading jitter performance and superior features to ensure the reliable transport of data, multimedia, and voice traffic.

Combining enhanced features such as flexible reference monitoring and exceptional holdover capabilities with jitter performance of <0.5ns, the ZL 30100/1 digital PLLs cost-effectively meet Stratum 3 and Stratum 4/4E requirements for access, edge, and customer premises equipment.

Darren Ladouceur, marketing manager for Zarlink's Timing and Synchronization, said, "Compared with competing devices, this new series of digital PLLs delivers superior performance and enhanced features for externally timed and line-timed systems."

On their inputs, both timing chips accept two references and automatically synchronize to any combination of clocks operating at 8kHz, 1.544MHz, 2.048MHz, 8.192MHz, or 16.384MHz. For equipment with access to multiple timing references, the chips ensure system reliability by monitoring references for accuracy. If a problem is detected, the devices' reference switching capability enables systems to switch between timing references to avoid a potential loss of services.

Suitable for use in central office and edge equipment requiring Stratum 3 timing, such as master DSLAMs (digital subscriber line access multiplexers) powering consumer broadband access, the ZL30101 PLL's holdover capability allows externally timed network equipment to receive and send data even when the network synchronization source is temporarily lost or interrupted.

Meanwhile, the ZL30100 timing chip allows designers to cost-effectively design a timing solution meeting Stratum 4/4E requirements for a range of line-timed equipment - from PBXs and remote access DSLAMs, to wireless base stations, enterprise routers and gateways. The device provides clocks meeting international standards during normal operation, and enhanced reference monitoring and reference switching capabilities that allow the PLL to switch the source of timing from a failed interface to an operational interface without losing data.

Paired with a 20MHz oscillator, the ZL30101 provides precise reference monitoring meeting Stratum 3 specifications. The ZL30100, with selectable reference monitoring, allows designers to choose from a range of cost-effective clock oscillators or crystals that meets their equipment requirements.

If the source of network synchronization is temporarily lost, both the digital PLLs switch automatically into holdover mode, and continue to generate output clocks based on data collected from past reference signals. The devices deliver a holdover performance of 0.01ppm for Stratum 3 systems, and 0.15ppm for Stratum 4/4E systems.

Offered in a 64-pin TQFP package measuring 10-by-10 mm, the ZL30100 and ZL30101 chips are priced at $10 and $20, respectively, for 1,000-unit quantities.





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