Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Mentor links SystemC to emulation

Posted: 20 Apr 2004 ?? ?Print Version ?Bookmark and Share

Keywords:mentor graphics? systemc? testbench? vstation? emulator?

Moving logic emulation to higher levels of abstraction, Mentor Graphics has announced a "transaction based" interface between SystemC testbenches and its VStation emulators. The interface is a new feature of VStation TBX, a "verification accelerator" that compiles RTL and behavioral Verilog testbenches directly into VStationPro emulators.

Duaine Pryor, principal engineer for Mentor's emulation division, said that VStationTBX can provide a 10 to 1,000-fold speed increase over traditional co-simulation techniques, where Verilog testbenches run on workstations. With the new capability, SystemC testbenches still run on a host workstation, but are connected to VStation through a transaction-based interface that supports the System Verilog Procedural Interface (VPI).

This connection, Pryor said, is much faster than previous connections using the Verilog Programming Language Interface (PLI). "This is the first non-PLI based coupling, the first true transaction-based coupling, between SystemC and the emulator," he said.

"In the past, with PLI-based coupling, SystemC ran very fast and the emulator ran very fast, but the connection between them was slow. What we're doing with the automated transaction-based connection is allowing them both to run at full speed."

Pryor said the connection makes it easier for designers to use SystemC testbenches, which not only run fast but offer features like directed random testing, concurrency, and a higher level of abstraction.

Pryor said that Mentor supports the Open SystemC Initiative (OSCI) reference simulator, and places no restrictions on SystemC code. In the future, he said, Mentor will support languages such as "e" and Vera in a similar manner. The VStationTBX SystemC capability is available now as part of Mentor's Scalable Verification Platform.

- Richard Goering

EE Times





Article Comments - Mentor links SystemC to emulation
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top