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Synopsys enhances SiVL verification tool

Posted: 14 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? sivl? verification tool? silicon-versus-layout? svl?

Synopsys Inc. has announced enhancements to its SiVL verification tool. The key component of the company's design-for-manufacturing (DFM) solution, the silicon-versus-layout (SVL) tool compares a target design to its simulated silicon image in order to verify that the design is manufacturable.

The silicon-correlated models, with new 'check-figure' capability and enhanced checking functionality ensure that key lithography induced errors are identified, all of which are essential for resolution enhancement technology (RET) closure. An RET closure is achieved when a design's layout matches its actual silicon image.

According to Synopsys, accurate lithography simulation reduces the risk of respins, which can save thousands of dollars in scrapped materials and months in production delays.

"The rapidly expanding use of RET in the 90nm and 65nm nodes dramatically increases the chances of killer lithography-related defects going undetected - which can easily result in weeks or months of product delay," said Sandeep Khanna, VP of marketing for Synopsys' Design for Manufacturing Group. "With the new version of SiVL, Synopsys is delivering a verification solution to find these defects to obtain RET closure and prevent such costly time-to-market delays."

Compared to 130nm designs, 65nm designs have up to 30 times more complex mask synthesis due to increased layout, model, and RET recipe complexity. To obtain accurate full-chip simulation, the SiVL tool utilizes the modeling technology from Synopsys' Proteus optical proximity correction (OPC) product. The 'check-figure' capability finds the critical features most likely to have errors before applying a combination of simulation-based lithography rule checks (LRC) to find real-world lithography errors.





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