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Toshiba to apply Sarnoff's TakeCharge IC design

Posted: 19 May 2004 ?? ?Print Version ?Bookmark and Share

Keywords:toshiba? takecharge? sarnoff? cmos? ic processes?

Toshiba Corp. has revealed that it will implement the TakeCharge on-chip electrostatic discharge (ESD) design approach from Sarnoff Corp. in its CMOS IC processes (0.18?m, 0.13?m, 90nm and 65nm process technology).

As part of the agreement, Sarnoff will also collaborate with Toshiba in order to develop customized solutions for future generations of Toshiba ICs in geometries as small as 45nm and 32nm.

TakeCharge technology has already been silicon-proven in Toshiba's CMOS products with advanced process technologies of 0.18um, 0.13um, and 90nm, and is currently being verified in 65nm.





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