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Startup offers new 'route' to IC design

Posted: 01 Jun 2004 ?? ?Print Version ?Bookmark and Share

Keywords:magma? monterey? cadence? silicon design systems? k-route tool?

Flouting conventional wisdom that maintains Magma, Monterey and Cadence offer the industry's finest physical-design tools, a new player in town is claiming to own the state of the art.

That's Silicon Design Systems, which plans to release its K-Route tool later this year. SDS says that K-Route will perform final placement, routing, timing, extraction and signal integrity simultaneously to complete tightly constrained designs faster and more predictably than today's popular design flows.

The startup is headed by onetime Quickturn marketing VP Naeem Zafar, who left the EDA industry for a few years to head a fingerprint sensor company, Veridicom Inc. Now SDS' president and CEO, Zafar leads 35 employees, most of whom are based at SDS' R&D center in Jerusalem.

SDS was spun out of Silicon Value Inc., a high-end ASIC design services house, in 2003. Zafar and investors bought out Silicon Value's internally built physical-design analysis and extraction tools, and secured an exclusive licensing agreement to commercially offer National Semiconductor Corp.'s routing tool.

Then SDS promptly smashed the router to pieces, Zafar said, and wove its own timing, extraction and analysis engines into the routing technology to create K-Route.

"At 180nm, wire dominance became the big problem. At 130nm, signal integrity became a problem, and as we drop to new process geometries problems are getting worse," said Zafar. "It used to take five to 10 weeks to get physical design done; now that has turned into 30 weeks."

Much of the delay is due to users trying to fix problems during post-layout optimization, he said. "Today, geometrical routing and timing, for instance, are often solved separately by separate tools with separate databases, sometimes coming from separate companies," Zafar said. "You solve one problem with one tool and solve the other with the other tool, but there is no guarantee they will converge-that problems solved in one will not cause problems in the other."

To get around this situation, users often build margin or slack into their designs, which can slow down the performance and expand die size, Zafar said. K-Route will help designers reduce margin using Afra, SDS' "fine-grained routing architecture," he said.

Every time users route a wire or via in a design, the SDS tool uses routing, extraction, timing and signal integrity analysis simultaneously to ensure the new elements do not adversely affect the rest of the design, he said.

Instead of making large iterations from routing back to placement, the tool uses a correct-by-construction method and performs routing iterations quickly at the wire and via level, rather than at the block level.

Users will feed the tool a rough placed netlist, and specify timing and physical constraints in industry-standard formats. K-Route will then do final placement and routing, driven with signal integrity and timing engines. The tool outputs LEF, DEF and GDSII.

"K-Route replaces four or five tools," said Zafar, who noted that customers will likely still use signoff tools to ensure their designs meet requirements, especially until they become more trusting of the new technology.

Multithreading option

Zafar said K-Route can be multithreaded to speed up overall routing time so that it can route a "large block overnight."

The tool works on a single data model and in-memory model. K-Route engines work together in tandem to route the design wire by wire, via by via, Zafar said.

"The benefit of our method is predictability in schedule, because once you have finished with our tool there is no need for post-layout optimization: You are finished with routing and you have converged the design."

Zafar said the tool will identify timing-critical signals, go to extra measures to reduce wire length on those signals and then route the rest of the signals that are not timing-critical.

"Similarly, we have a congestion map and a signal integrity engine that can identify areas that will likely cause problems, such as when signals run next to each other for a long time," he said.

The tool also has features for cell sizing, cell buffer insertion and elimination.

SDS will demonstrate K-Route at the 41st Design Automation Conference. The company hasn't yet released pricing.

SDS is currently seeking a second round of funding in anticipation of its product launch, which will likely come by year's end, executives said.

- Mike Santarini

EE Times





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