Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Physical design flow taps partition layout

Posted: 02 Aug 2004 ?? ?Print Version ?Bookmark and Share

Keywords:partition? physical design? asic? sta? pll ram?

This article describes a new hierarchical design flow and its usage on a 3 million-gate chip.

View the PDF document for more information.



Article Comments - Physical design flow taps partition ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top