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Altera hurdles 90nm challenges

Posted: 18 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:altera? stratix ii? cyclone ii? fpga?

Industry change is never easy. Either you adapt, or stay put and be left behind. With guaranteed huge earnings from the ASIC market, Altera Corp. did the former and came up with its Stratix II and Cyclone II families of FPGAs.

However, as with all kinds of change, it was not smooth sailing all the way. The transition to the 90nm mode has certainly not been easy, the company admitted, it has required more in-depth analysis, research and testing than prior nodes.

Before jumping over the 90nm fence, Altera collaborated with its foundry partner Taiwan Semiconductor Mfg Co. Ltd (TSMC) to address and resolve the 90nm and low-k challenges before entering production. As they developed and ran multiple test chips, they encountered three key challenges: interconnect, power management and design manufacturability.

Ben Lee, VP for Asia-Pacific region at Altera, said that they chose low-k to address the interconnect issue. "We decided early on that for 90nm to be successful, we have to use a mainstream process at TSMC," he said. "The reason why you want to use a mainstream process is because you can drive the yields up and the defects down quickly with volume."

Today, various 90nm companies are already using the low-k dielectric process because of its better yields and lower costs.

Designing from ground up

The second issue that needed to be addressed was power management. "When going to 90nm, there is a lot of leakage current because of the transistors, as they are so small and there are a lot of process-induced effects," Lee explained. To overcome this, they had to design for 90nm. "We had to re-architect the chip to fully take advantage of 90nm and design for power".

Lee added that engineers cannot just simply take a 0.13?m or 0.15?m design and quickly shrink it to 90nm. "It would be a disaster in terms of power," he exclaimed.

Altera and TSMC conducted a lot of tests on whether they would use double oxide or triple oxide based on performance and cost. Altera finally settled on the double-oxide process for all its 90nm projects. As they hoped and expected, it turned out to be a standard for 90nm.

The third challenge was design for manufacturability. "Design for manufacturability is not something where you just think about it before the design and then try to work/test for it after the exact design is done."

Altera had their engineers check for process limitations throughout every phase of the design cycle and made adjustments to every design stage to ensure enough design margins for the limitations. "It's one thing to design a chip and say 'we have this solution,' but it is another thing to be able to shift in volume," Lee remarked.

Variable inputs

Additionally, Altera developed a new logic structure called adaptive logic modules (ALMs) for its Stratix II to increase performance without consuming unnecessary power.

The company claims that ALM addresses the growing usage of adder functions in FPGA designs, such as in wireless technology and DSPs. "ALM gives you a variable number of inputs to choose from so you can maximize the use of the logic and the silicon," Lee said.

Presently, Altera is also focusing on its HardCopy devices, which are touted to be the industry's first structured ASICs that offer a comprehensive alternative to traditional ASICs. According to the company, the power consumption of these devices is on average 40 percent lower than the corresponding FPGA.

Commenting on other key players in the industry, Lee said, "Our competitors are about one year behind on 90nm and high-density FPGAs." He added that Altera has been doing for years what the other manufacturers say they are doing now in terms of modular blocks in FPGAs.

- Margarette Teodosio

Electronic Engineering Times-Asia





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