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Forte Design division unveils interactive timing analysis

Posted: 20 Oct 2004 ?? ?Print Version ?Bookmark and Share

Keywords:chronology? forte design systems? timingdesigner v7.0? timing analysis?

Chronology, a Division of Forte Design Systems, has released its TimingDesigner v7.0, which is an interactive timing analysis and diagram product. The press release states that this next generation release of TimingDesigner brings focus to the project management challenges of designing complex timing interfaces.

More stringent specifications for high speed designs means that timing analysis must now incorporate signal integrity and physical effects, as well as manage and monitor timing margins through the design process, the company said. The TimingDesigner allows users to model their timing challenges via timing diagrams and spreadsheet technology, and analyze a range of conditions to obtain accurate timing results. Designers can define timing constraints, evaluate timing parameters, create specifications, and analyze complex interfaces within their design.

According to Chronology, the TimingDesigner v7.0's new project manager simplifies the exchange of critical timing information and enables users to better manage the specification and analysis of high performance interfaces for their digital IC and board designs. To handle growing design complexity, designers now have the option to logically organize multiple diagram components within one project. Components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams. In addition, designers can also merge two diagrams from different components, automatically creating an interface that accounts for component connectivity as well as managing signal duplication and propagation delays.

"For timing-critical designs, we needed to provide our customers with a logical way to organize multiple timing diagrams as components within a single project," shared Jacquie Taylor, GM of Chronology. "TimingDesigner v7.0 offers designers a new way to manage complexity by aligning their timing plan in the same way they organize their designs, whether they are looking at interfaces between embedded functions on an ASIC or a programmable IC, or between devices on a circuit board."

Other enhancements

Aside from the new project manager, other enhancements are included in this release. Designers can now localize library management for specific diagrams and their associated paths, avoiding time-consuming network access to large library repositories. Additionally, to simplify analysis and save debug time, designers can now designate the use of only minimum or maximum values for their diagrams (as opposed to both minimum and maximum values) to perform best-case and worst-case timing analysis. Other enhancements include waveform dividers to visually group signals together; font modifiers to better support documentation style guides; display of decoded values on valid edges of signals, derived signals and buses; and built-in spreadsheet functions for improved analysis reporting.

TimingDesigner 7.0 is already available. Chronology offers several licensing options including perpetual and time-based. Pricing starts at $2,640 depending on the configuration. TimingDesigner is supported by Microsoft Windows, Sun Solaris, HP-UX and Linux platforms.





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