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Fast Fourier transforms speed up, stretch out

Posted: 16 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:ip? fpga? fast fourier transform? fft? wimax?

RF Engines Ltd has made a substantial intellectual property (IP) business out of creating signal-processing building blocks that are crafted for implementation in FPGAs.

The company offers a range of filters and other more specific building blocks off-the-shelf, and also provides custom-crafting services to fit a function into a particular performance range on a specific FPGA. A set of fast Fourier transform (FFT) blocks comprises one part of this increasingly important family.

The traditional market for FFTs is expanding, said Simon Underhay, technology sales executive for RF Engines (RFE). FFTs have been widely used since the invention of the algorithm to shift data sets between the time and frequency domains. Most often, this is done for spectral analysis. The move toward very wideband networking standards, such as WiMAX, and the speculation about ultrawideband communications has created an immediate need for wide-spectrum test equipment.

These needs have led RFE to introduce two new standard-product IP offerings: a HyperSpeed and a HyperLength FFT block. The two designs are built from existing IP in RFE's repertoire but achieve new levels of performance.

On the HyperSpeed side, RFE has designed a modular architecture that harnesses a number of FFT engines working in parallel and combines their results to produce real-time FFTs at enormous incoming sample rates: up to 3.2Gsamples/s. This in an FPGA, mind you.

The fundamental trick is to demux the incoming data and spread it across a bank of FFT blocks, Underhay explained. At these rates, it is necessary to use not only external ADCs, but also external demultiplexer chips designed for the purpose. This reduces the incoming data rate to something feasible for an FPGA, perhaps in the 200MHz range.

A second demultiplexing step reduces the data rate to the point that the data can be handled by the bank of FFT units. The results from these units are recombined in a complex multiplier bank and subsequent discrete Fourier transform block to produce a set of parallel outputs. The result is one of the first solutions--short of a rack full of filter banksfor looking at frequency-domain data extracted from multigigahertz signals in real time.

A quite different combination of blocks produces the HyperLength architecture. Underhay explained that in some emerging applications, resolution demands were so high that the traditional data lengths used in FFTsone to a few k sampleswere simply inadequate. But by exploiting the mathematics of integer transforms, it is possible to perform extremely long FFTs without enormous amounts of parallel hardware.

In the HyperLong architecture, a pair of pipelined FFT engines is used with a complex multiplier bank and an external memory. The memory is used cleverly to implement a corner-turn permutation to reorder the data. The combination of DFTs and reordering stages creates a long transform: up to about a million points with current external SRAM technology.

RFE notes that by using sdram for the external memory in combination with the internal SRAM resources on the FPGA, it is possible to implement even longer FFTs, but bandwidth suffers. The use of double-data-rate DRAM meant that RFE had to design its own rather specialized DRAM controller block as well, since real bandwidth in and out of the memory becomes the limiting factor in transform bandwidth.

The company offers two sample designs on its data sheet, one for a million-point FFT at 200MHz bandwidth and another a 256 million-point transform at 10MHz.

Since the designs are built from basic signal-processing blocks that RFE has carefully constructed for reuse, a HyperSpeed or HyperLength engine to fit a specific set of requirements can be configured by the company in a matter of days.

This kind of service makes life simple for the user. But Underhay noted that creating an FFT block from scratch should not be done lightly. Along with a detailed understanding of the algorithm, RFE has painfully acquired an understanding of FPGA architectures and the quirks of the design tools. "The tools have improved in recent years," said John Lillington, CEO and CTO of RF Engines. "But it's still necessary to learn to work around their limitations." Underhay offered as an example a recent design done on a Xilinx Inc. Virtex Pro device, in which 90 percent of the logic cells were used and the design achieved 190MHz operation.

Along with great skill, RFE employs on-the-fly reconfiguration in its architectures. Despite what many designers believe, on-the-fly reconfiguration does not require reprogramming the entire FPGA or substantially interrupting the flow of data through the device, Lillington said, and he anticipated increased use of the approach in the future.

- Ron Wilson

EE Times




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