Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Processors/DSPs
?
?
Processors/DSPs??

PCI mezzanine card packs ADSP-TS201 TigerSHARC bite

Posted: 30 Nov 2004 ?? ?Print Version ?Bookmark and Share

Keywords:bittware? dsp? analog devices? dsp? silicon?

Board maker BittWare Inc. now has a DSP board based on Analog Devices Inc.'s (ADI) DSP silicon. In fact, the company's new T2-PMC (T2PM) multi-processor PCI Mezzanine card packs no less than four ADSP-TS201 TigerSHARC DSP chips. Moreover, the T2-PMC is now the third addition to BittWare's T2 family of TigerSHARC boards.

In addition to its 600MHz TigerSHARCs, the T2PM features a Xilinx Virtex-II Pro FPGA, a 64bit 66MHz PCI interface, and a large on-board memory array. It also offers over 4GBps of high-throughput I/O interfaces.

It's scalable

To take advantage of the TigerSHARCs, the board also has a scalable architecture. Dubbed ATLANTiS (Advanced Transfer Link Architecture for New TigerSHARC), the architecture is what's responsible for letting you seamlessly configure your hardware via software.

By tightly integrating the DSPs, PCI bridge, PMC interface and I/O peripherals with the board's on-board FPGA, ATLANTiS gives you any number of options for configuring and routing its high-throughput I/O.

A single cluster of four ADSP-TS201 TigerSHARC DSPs is interconnected by a 64bit 83.3MHz bus. With a total of 14.4GFLOPS (3.6 GFLOPS per DSP; floating point operations/s) of floating-point processing power, the TigerSHARC's SuperScalar architecture also lets the T2PM board achieve 57.5BOPS (14.4 BOPS per DSP; billions of operations/s) of 16-bit fixed-point performance.

Inter-processor communications ring

This processing performance is integrated with 24Mb of on-chip RAM per DSP, and four high-speed LVDS (low voltage differential signaling) ports, running at up to 1GBps each. The T2PM interconnects two link ports from each DSP to create an inter-processor communications ring, while the other two are routed to the on-board FPGA for I/O.

The T2PM also packs lots of off-board I/O bandwidth (over 4 GBps) and I/O options. These include eight LVDS link ports, the PMC form-factor with BittWare's PMC+ I/O extensions, and eight Xilinix RocketIO high-speed serial transceivers, with a total potential I/O bandwidth greater than 6GBps.

The aforementioned ATLANTiS architecture, implemented in the on-board Xilinx XC2VP30 Virtex-II FPGAs, adds flexibility to the T2PM, letting you perform pre-processing, post-processing, and co-processing, as well as configure and route the off-board I/O.

In addition to that, a BittWare SharcFIN PCI bridge interfaces the DSP cluster to the local 64bit 66MHz PCI bus. The SharcFIN also provides host access to the DSP, as well as interrupts, flags, an on-board bank of SDRAM (up to 256MB worth), 8MB of boot flash, and the FPGA control registers.

Software support

BittWare's BittWorks software tools provide host interface libraries, as well as a variety of diagnostic utilities and configuration tools for this board. BittWorks also includes debug tools. BittWorks also includes TS-Lib optimized libraries for TigerSHARC and the popular TigerSHARC BSP for Gedae.

Third-party tools are also available to support BittWare's ADSP-TS201 boards, including ADI's VisualDSP++ and SDL's DSPdeveloper target for MatLab and Simulink.

Realtime operating systems available include ADI's VDK (VisualDSP Kernel), and Enea's OSEck RTOS (realtime operating system).

BittWare says its T2-PMC will ship early next year (2005) with pricing starting at about $8,600. A 6U VME ADSP-TS201 board will also be available.

- Alex Mendelsohn

eeProductCenter




Article Comments - PCI mezzanine card packs ADSP-TS201 ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top