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Falanx targets handheld graphics

Posted: 04 Feb 2005 ?? ?Print Version ?Bookmark and Share

Keywords:cellphone? personal communications? video? cpu? handset business?

The notion that a cellphone can be the point of convergence for personal communications, photography, video and gaming poses an interesting architectural problem: Each of these functions has its own computationally-intensive algorithms.

Given the current power of embedded CPUs for the handset business, each requires a certain amount of hardware acceleration to provide adequate performance.

Some argue that because of small screens and limited resolution on handset displays, the computational problem for imaging algorithms is actually not critical and can be handled with a general-purpose CPU. But some graphics experts argue the opposite.

Borgar Ljosland, CEO of graphics startup Falanx Microsystems said he sees it this way: "We are already seeing camera and game applications on handsets. Maybe right now they look crappy ! the games are just time-killers, not compelling experiences like those on the Gameboy. But the applications are coming.

"The driving force," Ljosland continued, "isn't market demand. It's that the handset manufacturers and the service providers all need for people to buy new handsets. But especially in the U.S. ! less so in Europe and Asia ! the service providers aren't willing to invest in the network infrastructure that would enable a new generation of network capabilities in the handsets. So to keep the market moving, the handset designers are putting in more network-independent features. Today that means still cameras, video clips and games.

Cellphone displays continue to lag. "We may not see 200 dot-per-inch displays until the end of this decade, and then only in high-end handsets," Ljosland added. "In the meantime, it takes aggressive image processing ! especially anti-aliasing ! to provide a good-looking image on those little screens. In the past, anti-aliasing has meant lots of computation and lots of memory bandwidth."

Hence, designers face the prospect of several hardware accelerators, each with significant memory bandwidth needs, and each idle most of the time. This is daunting scenario, experts agreed.

Falanx is offering one possible solution. The company, spun off from a university research project and venture funded, has developed a graphics pipeline with several very distinctive characteristics.

First, is the low-power design targeting hand-held devices. Second, it is organized from the algorithm level down to the RTL to minimize memory traffic, reducing both the footprint and the energy required by volatile data. Third, the pipeline is based on computational patterns, rather than fixed functions. These patterns are common to a number of different algorithms, including 3-D computations and MPEG compression.

"This allows us to reuse essentially the same gates for 3-D graphics and for video display," Ljosland said. "That of course reduces the total gate count significantly."

Ljosland said that in the research phase, the architecture had been fully programmable. As his design team focused in on graphics and video, the design began to resolve itself into two somewhat programmable blocks: a geometry engine and a pixel processor. It was found that the pixel processor hardware could be used for motion estimation, and with some added cleverness the geometry engine could implement a discrete Cosine transform - the two components at the heart of MPEG and H.264 compression. So the same hardware can perform either video compression and decompression or 3-D rendering, or both simultaneously at reduced performance.

The gate count for the pixel engine is at least 190,000 gates, depending on options. In 130nm Taiwan Semiconductor Manufacturing Co. Ltd. CMOS process, that comes out to about 4.5 mm2, exclusive of memory. The geometry engine adds about another 150,000 gates, for a typical total gate count of perhaps 350,000 gates. In addition the engine needs about 7 KBytes of sram, mostly single port.

Falanx has licensed an early version of the architecture to Zoran, and is now readying for production the second-generation design. Known as the Mali architecture, the IP can offer handset developers significant reductions in power consumption, gate count and memory usage, according to Ljosland.

- Ron Wilson

EE Times





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