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Latest Xilinx FPGA design tool aims to boost performance

Posted: 26 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? field-programmable gate array? fpga? design tool? analysis tool?

Xilinx Inc. released early this week the next generation of the company's field-programmable gate array (FPGA) design and analysis tool, PlanAhead 7.1.

According to Xilinx, the tool enables designers to boost logic performance by 15 percent and, in some cases, double performance for Xilinx high-density FPGA designs. PlanAhead 7.1 includes several new features designed to help users achieve up to 50 percent faster timing closure, the company said.

PlanAhead is used between synthesis and place and route, allowing designers to analyze and modify each individual design block. Blocks can then be stitched together in a final assembly phase.

The PlanAhead 7.1 tool supports all leading-edge Xilinx FPGA families, including the Virtex-4 Platform and Spartan-3 Generation. The tool supports Windows 2000 and Windows XP, Red Hat Enterprise Linux 3, and Solaris 2.8 and 2.9. PlanAhead 7.1.

Xilinx said PlanAhead 7.1 is available for use with the Xilinx Integrated Software Environment (ISE) 7.1i FPGA design suite. The PlanAhead 7.1 tool is being offered at a promotional price of $5,995, the company said. A demonstration of PlanAhead 7.1 is available on the company's website.

EE Times




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