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Semiconductor technologies for power management (Part 3)

Posted: 27 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:power management? small signal transistor? transistor? semiconductor ic? bipolar npn transistor?

Semiconductor technologies for power management (Part 3)

By Reno Rossetti
Fairchild Semiconductor Inc.

A monolithic process example
Power management integrated circuits come in different varieties. If we narrow them down to voltage regulators, we still need to distinguish controllers from fully featured voltage regulator ICs that incorporate on-die the driver stage and power transistor. Controllers can be designed in every possible process technology, however true monolithic regulators require specialized processes capable of integrating signal and power transistors on board. In this section we will focus on this class of specialized power IC processes.

One such process is the Bipolar-CMOS-DMOS (BCD) process, capable of integrating bipolar transistors for precision applications, with CMOS for dense signal processing and DMOS for power handling. Figure 10 shows a cross section of a generic low voltage BCD process. Naturally Figure 10 shows the power of a monolithic planar process that is able to offer an impressive variety of devices all on the same surface of a die, all obtained at the same time, and with a single construction process. This process is suitable for many applications including motherboard DC-DC voltage regulator applications.

PMOS transistor

Figure 10: Cross section of low voltage BCD process (Click to view full image)

Packaging
Silicon dies must be enclosed in packages for protection and handling. IC packaging is a very important subject and can be as or more challenging than the IC design itself. For example, a package that lets moisture in will soon render the chip inside useless. In modern portable applications like cellphone handsets the challenge often is to have a package that is no bigger than the die itself, hence the emerging popularity of chip-scale-package (CSP) like the one illustrated in the upper right corner of Figure 11. In high power applications heat dissipation is a crucial issuethe package is often the narrow bottleneck through which heat has to escape from the die and hence its thermal resistance has to be minimal like in the TO220 package illustrated in the lower right corner of Fig.11. In between we find a slew of package shapes and forms that fit the intended application, delivering proper power, voltage, current, or size characteristics.

PMOS transistor

Figure 11: Package options vs. target systems (Click to view full image)

Discrete power technology: processing and packaging

Introduction
Microprocessors for PCs are at the forefront of the computing industry, leading with huge nano-scale chips built in multi billion dollar fabrication plants. So far, the success of the semiconductor industry has been assured by Moore's law, which states that the number of transistors per given area will roughly double every two yearsa concept that underscores the fast-paced dynamic of the industry. However, new chips in smaller footprints are upping the trend for increasing power densities to amazing levels. At every new technology juncture, the CPU becomes denser and hotter. Keeping pace with changing densities, compounded with the need for disposing the resulting heat, is creating more challenges for applications designers.

Providing power from the AC line is also becoming an issue for designers. The number and growth rate of electronic appliances is driving a huge demand for power; prompting concerns for power distribution and energy conservation and spurring a slew of protocols and initiatives aimed at minimizing the waste of power. These requirements are pushing technology advancements beyond the traditional, cost-oriented model of minimizing the appliance's Bill of Materials (BOM) to look for new solutions.

At the core of all power management solutions, from the wall to the board, are power transistors. Evolving discrete semiconductors is essential for supporting Moore's law, and thereby maintaining the industry's healthy growth. Not surprisingly, designing and mass producing cost-effective discrete transistors capable of efficiently handling power requires increasingly sophisticated semiconductor processes and packaging.

From wall to board
Electric power is transferred to the CPU in two crucial steps: from the high voltage AC line to an intermediate DC voltage and, from there to the low voltage regulator (VR), which is needed to power the CPU. The high voltage "planar technology" transistor underlying this AC-DC conversion must sustain voltages in the 600-700V range and few Amperes of current; meanwhile, the low voltage "trench" transistor powering the CPU has to handle a few volts with hundreds of Amperes. Both conversions have to be accomplished with the lowest possible power losses. It stands to reason, then, that such diverse performance requirements are satisfied by two quite different discrete MOSFET transistor technologies, "planar" for high voltage and "trench" for low voltage.


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