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Credence, Cadence validate flow for faster yield diagnostics

Posted: 20 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:credence systems? encounter test? 90nm? sapphire test platform?

Credence Systems Corp. has validated a yield improvement flow between their Sapphire test platform and Cadence Design Systems Inc.'s Encounter test. Sapphire supports Cadence Encounter test true-time delay test patterns, which are STIL based, as well as Cadence Encounter diagnostics input format for capturing test failures from Sapphire. The validated flow reduces test escapes and improves the speed for defect resolution in designs using 90nm or less.

Delay testing is critical for nanometer-scale designs as defects cause slow transitions. At-speed delay testing is intended to detect these problems, but as many as 50 percent of these defects can escape detection because they are tested on non-critical paths. Also, traditional at-speed fixed-time ATPG does not constrain the test patterns to the capabilities of the tester, so in many cases, test patterns violate tester pin timing and have to be discarded. The combination of these two limitations results in substantially lower product quality and slower time to manufacturing test.

"Delay defects are a dominant cause of yield loss in designs at 90nm," said Dave Ranhoff, president, CEO at Credence.

A Sapphire used in conjunction with Cadence Encounter True-Time Delay Test as well as Cadence Encounter Diagnostics provides semiconductor companies an optimized engineering and production test development path for detecting and diagnosing these most difficult problems. Supporting the design for yield methodologies developed by the major EDA suppliers like Cadence is important to our customers and fits into our broader vision of how Credence participates in design debug all the way to production test, added Ranhoff.

"At 90nm the major issue facing manufacturers is to quickly resolve subtle design-process interactions that are not predictable before actual silicon and that are difficult to isolate within silicon," stated Sanjiv Taneja, group director at Cadence Design.

Traditional ATPG-based diagnostics tools are typically less than 40 percent accurate at 130nm and do not support volume operation, dynamic diagnostics, customizable fault modeling, or vectors generated by other ATPG tools, Taneja said.





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