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Fujitsu to ship structured ASIC built using Cadence

Posted: 03 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:asic? quality-of-silicon? encounter? accelarray?

Cadence Design Systems Inc. and Fujitsu Microelectronics America Inc. (FMA) will ship initial production volumes of structured ASIC using Cadence Encounter digital IC implementation this month. Encounter, which was originally developed for standard ASICs, provided rapid timing closure with signal integrity for optimal quality-of-silicon (QoS) in the implementation phase of the design flow for FMA's AccelArray family of structured ASICs.

"We chose the Encounter platform as the netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility in implementing standard ASIC and structured ASIC designs," said Noboru Yokota, senior director of engineering at FMA.

The design incorporates 3.5 million logic gates, 119 instances of 2RW SRAM (40bx512w), 33 instances of register file (40bx32w) and 12-channel, 3.125G SERDES for high-end servers developed for consumer applications. The design was completed with low, non-recurring costs by using AccelArray Giga Frame.

The Fujitsu AccelArray Giga platform addresses the specific needs of mid-volume vertical markets that require the performance of cell-based ASICs. These platforms leverage Fujitsu's decades of ASIC design and system-level expertise in the networking, storage networking, next-generation consumer electronics and imaging markets. Giga platforms reduce back-end physical design time such as DFT insertion, power mesh, clock tree synthesis and simultaneous switching output (SSO) analysis, all of which can consume a considerable amount of time. The Giga platform offers up to 75Gbps of full-duplex SERDES aggregated bandwidth by incorporating pre-diffused universal G-PHY macro cells.

SoC Encounter GPS combines RTL synthesis, silicon virtual prototyping, and full-chip implementation into a single system. It enables engineers to synthesize to a flat virtual prototype implementation-including full-chip, routed wires-right at the beginning of the design cycle. With SoC Encounter GPS, engineers have an early, accurate view of whether the design will meet its targets and be physically realizable. Designers can then choose either to complete the final implementation or to revisit the RTL design phase.





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