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Water-filled wafers streamline chip cooling

Posted: 16 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:microelectronics advanced research corp.? chip cooling? water-filled wafer? self-cooling pcb? flip-chip-mounted ic?

Georgia Institute of Technology researchers have developed a chip-cooling process that they hope will replace the bulky, bolt-on metal towers used with microprocessors like the G5. Instead of an entire tower through which water circulates, they have created water-filled wafers that can be integrated on self-cooling PCBs.

The boards, which are being fabricated by the Microelectronics Advanced Research Corp. (Marco), will provide the plumbing for flip-chip-mounted ICs. In the streamlined cooling system envisioned by researchers, water will circulate through the silicon substrates of microprocessors and other system-level chips by virtue of trenches etched on the otherwise unused backside of the wafer.

"We have applied for patents with Marco, and so far, we have garnered interest in licensing our technology from over a dozen major semiconductor makers," said Bing Dang, Georgia Institute of Technology EE. The researcher co-invented the technique with professors Paul Kohl and James Meindl and their research assistants Paul Joseph, Muhannad Bakir and Todd Spencer.

Although the technique is still in the prototype stage, the engineers have succeeded in fabricating very deep trenches that are only about 100m wide in the backside of wafers. Normally, that side remains unused, but the new technique uses almost the entire surface area of that side for cooling. Because the water circulates through the silicon chips themselves, which have good thermal conductivity, the approach promises to cool chips much more efficiently than the customary metal cooling towers.

"Eventually, you could integrate microelectromechanical pumps onto advanced PCBs, but our approach is flexible enough that it could be directly connected to the pumps already being used by Apple's G5 computers," said Dang.

The technique works entirely at low temperatures, so that it can be performed during packaging, after the front side of the wafer has been fabricated. After the trenches are etched in the backside of the wafer, they are filled with a sacrificial polymer, Dang said. "Then we layer a porous overcoat above the trenches and heat the wafer to about 200C, which vaporizes the polymer through the overcoat, leaving the trenches empty." Sealing the trenches with another polymer after curing makes them watertight.

"Next, we etch holes through the sealing polymer that are aligned with the trenches and use a photodefinable polymer to create micropipes that match orifices on the board," said Dang.

The chips are then diced up and flipped over, and the normal solder bumps are added for traditional flip-chip packaging. Then they are mounted on a water-filled circuit board using the normal encapsulation technique.

"The beauty of our approach is that the normal solder bumps are alongside the micropipes, and they all get sealed to the board at the same time using flip-chip encapsulation and bonding," thus connecting the chip electrically while its cooling system is sealed, said Dang.

For future low-cost organic package substrates, according to Dang, the technique also promises to enhance the reliability of chips not only by controlling the average operating temperature, but also by eliminating the hot spots that would otherwise inevitably result from the different thermal expansion rates of silicon chips and polymer packaging.

Traditional liquid-cooling techniques, which circulate liquid through separate cooling modules, have less efficient heat transfer, according to Dang. Other techniques can also damage chips by requiring bonding temperatures that range from 400C to 700C, Dang said.

The researchers have tested the trenches and found that they can withstand pressures of up to 35 pounds per square inchmuch higher than what the circulating cooling liquid would actually require. By Dang's calculations, the technique will be able to cool about 100W/cm?.

The technique will initially be used on conventional chips, but could eventually be integrated into advanced 3D packaging modules that are now only on the drawing board, Dang said.

The research was sponsored by Marco and the U.S. government's Defense Advanced Research Projects Agency.

- R. Colin Johnson

EE Times




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