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Pentek beefs up GateFlow FPGA IP Library

Posted: 01 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:pentek? gateflow fpga ip library? digital downconverter? ddc? xlinx?

Pentek Inc. announced an addition to its GateFlow FPGA IP Library that implements a 256-channel narrowband digital downconverter (DDC). Designed for use in Xilinx's virtex ii, virtex ii pro or Virtex 4 FPGAs, the Model 4954-430 core utilizes a unique architecture to achieve 64 times the channel capacity of conventional quad asic downconverters. This intellectual property (IP) core is suitable for developers of applications requiring a high number of digital downconverter channels with size, weight, cost and power constraints, such as military radios and commercial wireless.

"This represents a huge boost in channel density, " said Rodger Hosking, VP of Pentek. "In the past we have been limited to just a handful of DDC channels in a single device. The Model 4954-430 core delivers an extremely high channel-to-FPGA ratio, with density at least an order of magnitude higher than any other implementation available in either FPGA or ASIC form."

Accepting real or complex data samples at rates up to 185MHz, the architecture utilizes a channelizer stage that generates 1,024 fixed adjacent frequency channels with alias-free performance greater than 75dB across the passband of each channel. A 256-output switch matrix follows the channelizer, providing a coarse tuning capability for the desired output channels, added Pentek.

Each of the 256 DDCs has a programmable numerically controlled oscillator (NCO) to implement independent fine-tuning for each channel and mixer to translate the signal of interest to baseband. A decimating FIR low-pass filter then defines the channel bandwidth of the baseband output. The NCOs have a frequency resolution of 32bits, and the baseband outputs pass through a programmable gain stage before being rounded to their final 16bit result. Each channel has an independently programmable 16bit gain control.

The decimation factor setting is common to all channels and is programmable from 1,024 to 9,984 in steps of 256. Decimation filter coefficients are user-programmable in RAM structures, and a complete set of factory-default values are supplied for an 80 percent passband response filter for all 35 decimation factors. For an input sample rate of 185MHz, the resulting output bandwidth ranges from approximately 14.8kHz to 144kHz.

The Model 4954-430 IP is priced at $14,995 with delivery from 8 to 10 weeks ARO. To simplify the acquisition process, the GateFlow IP Core Libraries are offered under the standardized SignOnce IP Project License, the industry's first multi-vendor common license for FPGA-based IP. The core is also available as a factory-installed option on several of Pentek's FPGA boards.




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