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Designing with ultra-low voltage MOSFET arrays

Posted: 05 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:analog? mosfet? electrically-programmable threshold? epad? mosfet?

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Low power and "NanoPower" operation

When supply voltage decreases, the power consumption of a given load resistance decreases as the square of the supply voltage. So one of the key benefits in reducing supply voltage is to reduce power consumption. Although usually decreasing power supply voltages and power consumption go hand-in-hand with decreasing useful AC bandwidth and increasing noise in the circuit, a designer can make the necessary tradeoffs for a given circuit application and bias the circuit accordingly to optimize a number of variables.

From the previous paragraphs a scenario emerges where low supply voltages, in conjunction with the appropriate EPAD MOSFETs and careful circuit design to bias different branches of the circuit optimally, a circuit can be designed so that power consumption can be minimized to previously unattainable levels.

A circuit can be designed using different members of the EPAD MOSFET family so that power consumption is minimized for each intended circuit function. Circuits operating in microwatt or even nanowatt mode can be built and still provide a well-biased and tightly controlled circuit function.

In power critical applications, this power reduction can result in more than a hundred-fold or thousand-fold power consumption reduction, when compared to conventional circuit methods. Potentially nanopower circuits may alter the power source requirements in many applications and enable a breakthrough in power management and portable system design.

EPAD MOSFET basic circuits and examples

An EPAD MOSFET is an active device that can be used as a basic circuit element in a great number of designs. There are many circuits where they can be used to advantage. The number of potential designs and uses using these EPAD MOSFET devices are limited only by the designer's needs and imagination.

In selection of a particular member of a product family, there are usually one, two or more specifications or features that are of overriding importance for a specific application. As the threshold voltage Vgs(th) is a basic device specification, its selection determines quite a few key parameters that may be fundamental to the way a design is implemented.

Some of these key parameters and considerations include:

1. The voltage level relationship between input and output voltages

2. The desired operating voltage of the power supply (or multiple supplies)

3. The desired frequency response

4. The required signal to noise ratio

5. The desired quiescent current of the design

6. The overall power consumption

7. The output drive and other output characteristics, such as voltage swings, currents, etc.

Once the key factors of a system are determined, one or more suitable members of the EPAD MOSFET family can be selected. Different Vgs(th) devices may be used for different functional blocks.

The following are a few of the basic type of circuits that highlight the capabilities of this product family.

Parallel connections

EPAD MOSFET arrays lend themselves to easy parallel connections. For example, an ALD110800 can have all the 4 drain terminals shorted together, all the 4 source terminals shorted together and all 4 gates tied together in a parallel connection. The device becomes connected as a single MOSFET device with 4 times the current output. Likewise, a dual EPAD MOSFET can be wired in parallel as a single MOSFET to produce double current output.

EPAD MOSFET isolation & (diode) clamping circuits

Many circuits require an isolation of their inputs and input impedance from that of the output impedance so that the output loads do not interfere with the input signals. This can be accomplished sometimes by using a transistor buffer or an op amp buffer, each presenting a number of design tradeoffs. Using the ALD110800 zero threshold MOSFET, for example, one can provide this isolation and yet provide the output of a circuit biased to a voltage level that is in the same range as the input level. This is a fundamental ability of a zero threshold MOSFET. The input and output levels can also be biased around a fixed voltage, such as 0.0V.


Figure 4

Designing an application where input and output levels are at the same levels would be cumbersome without an ALD110800 and would require many components and support circuitry. The use of an operational amplifier in the unity gain mode could do the job, but might also introduce many of the shortcomings associated with using an operational amplifier. When some of these shortcomings become serious limitations, the designer must instead consider using a simpler circuit with a discrete MOSFET such as an EPAD MOSFET.

Another type of a basic circuit is a diode clamping function. For this type of application, one might consider using an ALD110902 or an ALD110900 EPAD MOSFET, which start conducting current right at 0.20V or 0.00V respectively. Since these EPAD MOSFETs exhibit high drain current versus drain voltage characteristics resembling that of a diode turn-on characteristic, a diode clamping circuit with tightly controlled operating characteristics can be easily built by connecting the drain and the gate terminals, as shown in Figure 4.

EPAD MOSFET inverter and buffer

A basic EPAD MOSFET inverter consists of either a resistor or a MOSFET load and an EPAD MOSFET as the inverting device. By selecting a device with a different Vgs(th), it is possible to create an inverter running at ultra low voltage levels, ultra low power levels, or both. There are infinite numbers of possible combinations of voltage and power levels with various Vgs(th), with the choice determined by the mission of the circuit.

In Figure 5A there are a couple of examples to illustrate some of the possibilities. In the first example, the basic inverter is powered with a V+ of only 200mV, with I+(max) = 0.24?A, resulting in an average power of about 25nW, assuming a 50 percent duty cycle signal. Another example of this basic inverter changes the Vgs(th) to 0.4V and load resistor to 44 megohms, resulting in the average current of 2.3nA and power of 0.45nW, using the same 200mV supply.

Using the basic inverter as a buffer provides high level of isolation between the input and output. The input bias current to the inverter is specified at 5pA typical and 30pA maximum. The input voltage can be biased at a level convenient for the input source. For example, if the input source is a 50mV peak to peak signal, centered around ground potential, then using ALD110800 Zero Threshold EPAD MOSFET may help eliminate an input level shift stage and the associated noise and distortion that such a intermediate stage can add to the signal. In a second example, where the input is a modulating signal, a depletion mode EPAD MOSFET is used to help bias the output to a desired voltage level and output impedance.


Figure 5A


Figure 5B

The output level in a basic buffer can be designed to produce the proper output voltage range in part by using an appropriate load resistor and by selecting a specific member of the EPAD MOSFET family. The output voltage can be biased and shifted to any voltage output level and output swing range by design.

The basic inverter can also function as a crude inverting amplifier by biasing the EPAD MOSFET transistor in the linear region. This inverting amplifier function is easier to implement using low threshold devices such as the ALD110802 (Vgs(th) = 0.2V) or the ALD110800 (Vgs(th) = 0.0V). As an example of a suggested biasing scheme, the output load resistor can be selected so that the output voltage is nominally at V+/2 when Vin = 0.0V. This type of inverting amplifier can produce 5x to 12x gain.

A simple voltage source using a EPAD MOSFET can be implemented with an EPAD MOSFET connected as a source follower where the output currents are supplied by drain to source currents (Figure 5B). This circuit is analogous to the classic emitter follower using a bipolar transistor. In this case the input (source) voltage and its source impedance are completely isolated from the output voltage and output currents due to the extremely high input impedance of the MOSFET. The impedance transformed Vout and Iout are dependent only on the input voltage and the output impedance of the EPAD MOSFET.

EPAD MOSFET logic gate

By extension to the basic inverter, a simple logic gate such as a NAND and a NOR gate can be readily implemented using EPAD MOSFETs. While digital logic circuit implementation is not the primary application focus for the EPAD MOSFET family, there may be situations where an unconventional logic function that operates on 0.4V or less power supply is useful.

In Figure 6 and 7 the EPAD MOSFET family devices are configured to implement logic functions. A single EPAD MOSFET quad array can be used to implement both NOR and NAND gates connected in a compound configuration. Figure 6 illustrates a two-input NOR gate and Figure 7 illustrates a two-input NAND gate.


Figure 6


Figure 7

A key consideration in designing EPAD MOSFET logic is to determine the V+ supply available which will power up the logic circuit. When the V+ supply voltage drops to below 400 mV, EPAD MOSFETs are actually likely to be always in the same "off-state". They are biased in the subthreshold region, whether in the "1" state or the "0" state of logic.

For example, consider the case of a 200mV supply and an EPAD MOSFET with threshold of 0.20V (ALD110802). In the output "1" state, the output is near 0.2V and the EPAD MOSFET is operating in the low end of the sub-threshold region, with drain current of about 19nA. In the output "0" state, the EPAD MOSFET is operating in the high end of the subthreshold region, with a drain voltage near 0.0V and a drain current of about 230nA. When multiple EPAD MOSFETs are connected to build logic gates, both the "0" state current and voltage levels and the "1" state current levels must satisfy the desired output voltage and operating temperature range criteria.

The drain current in any circuit configuration depends on the actual circuit topography. The operating frequency of such a logic gate implemented depends on the operating voltage and the amount of current switching between the "1" logic state and the "0" logic state.

As the supply voltage decreases below 0.2V, the available voltage and current margins for the logic switching decreases accordingly, and the environment where such a logic gate can be used become more limited and critical. At 0.1V supply, for example, the voltage noise margin between "1" and "0" state drops down to about 50mV after the first inverter stage. After several more inverter stages, however, this voltage noise margin gradually drops to about 20mV.

Factors to consider in designing logic function are:

? threshold voltage and device output tolerances;

? power supply voltage tolerances;

? output voltage level ranges defined to be acceptable for "1" and "0" levels;

? operating temperature ranges; and

? number of logic stages and the noise margins required.

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