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How to interface DDR-II SRAMs with Stratix II devices

Posted: 08 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Cypress?

Now that the uncertainties are established, we check the set-up and hold time margins for write operations at the memory input pins. For a 267MHz operation, the bit period is (3,750 ps/2) = 1,875ps. The Cypress DDR-II SRAM device has set-up and hold time requirements of 350ps at this speed.

Given these parameters, the set-up and hold margins for 267MHz DDR-II in Stratix are as follows:

Set-up time margin is the least when the data arrives late and the clock arrives early. Set-up time margin is calculated as:

TSU_MARGIN = tSHIFT_MIN - t,DS - tDCD - tIOSKEW - tEXT = 787.5 - 350 - 187.5 - 160 - 50 = 40ps

Hold time margin is the least when the data arrives early and clock arrives late. The margin is calculated as:

TH_MARGIN = tCK / 2 - tSHIFT_MAX - tDH - tDCD - tIOSKEW - tEXT = 1875 - 1087.5 - 350 - 187.5 - 160 - 50 = 40ps

The total margin available is the sum of the set-up and hold margins = 80ps.

Table 2 shows timing margins of a Stratix II EP2S60 interfacing with 267MHz and 250MHz DDR-II SRAMs for write operations when the board trace variations for the DQ and K/Kn pins are 50ps (approximately 0.3-inch of FR4 trace length variations). A similar timing analysis for other interfaces can be performed with a different FPGA and DDR-II SRAM device combination by replacing timing specifications from the corresponding data sheets.


Table 2

Read cycle timing

The FPGA controller sends the read request and address signals to the DDR-II SRAM device along with the K and Kn clocks in a similar manner to the write data. Therefore, the write timing parameters apply to these signals as well. Additionally, when the DDR-II SRAM device sends read data back to the FPGA controller, the design must meet the FPGA set-up and hold times.


Figure 7

Stratix II Read Cycle Timing DDR-II memory reads in Stratix II devices are implemented using the CQ echo clock output from the DDR-II SRAM. The CQ echo clock signal is directly fed into a DLL to centrally align the clock with the input data (DQ). This is achieved by implementing a phase shift on the DLL and using this phase-shifted clock to latch data from memory in the DDIO registers.

In the following exercise, the timing for a read operation from a Cypress CY7C1518V18-267 burst-of-2 267MHz DDR-II SRAM device to the Stratix EP2S60 device is analyzed.

Start the analysis by studying the relationship between the echo clocks (CQ, CQn) and read data (DQ) signals from the DDR-II SRAM. For the CY7C1518V18-267, the data clock-to-output (tCQD) and data hold times (tCQDOH) with respect to the echo clocks are 300ps and - 300ps, respectively. Hence the data valid window at the DDR-II SRAM device pins is 1,275ps (1875 - 300 - 300). Figure 8 illustrates these delays and other uncertainties in a read cycle timing waveform.


Figure 8

Board trace delays on the CQ/CQn signals and data bus can be ignored if the trace lengths are matched (=L2 in Figure 4). This timing analysis allows for a maximum board skew of 50ps between these lines. Due to this skew, the data valid window is further reduced to 1,175ps.

The next step is to analyze the set-up and hold margins for latching the read data (DQ) signals at the FPGA's DDR input pins. The echo clock, CQ, from the DDR-II SRAM is connected to the dedicated reference clock input pin of the DLL. This read DLL phase shifts the clock to centrally align the clock's edges to the data (default phase shift of 90). Uncertainty is introduced on read clock by the Stratix II DLL in the form of jitter (100ps).

Worst-case set-up and hold time requirements from the Stratix EP2S60 are 210ps and 180ps, respectively. These numbers were obtained from Quartus II timing analyzer reports. While performing timing analysis for a specific design, obtain the requirements from the Quartus II timing analyzer. Additional FPGA specifications that need to be taken into consideration are DLL phase shift error and DQS-DQ internal skew.

Given these parameters, the set-up and hold margins for 267MHz DDR-II in Stratix II are as follows:

Set-up time margin is the least when the data arrives late and the clock arrives early. Set-up time margin is calculated as:

TSU_MARGIN = tDLL_PS - tJITTER - tPSERR - tDQDINT - tEXT - tSU - t CQD = 937.5 - 50 - 0 - 80 - 50 - 210 - 300 = 247.5ps

Hold time margin is the least when the data arrives early and clock arrives late. The margin is calculated as:

tH_MARGIN = tCK/2 - tCQDOH - tH - tEXT - tDLL_PS - tJITTER - tPSERR - tDQDINT = 1875 - 300 - 180 - 50 - 937.5 - 50 - 0 - 80 = 277.5ps

The total margin available is the sum of the set-up and hold margins = 525ps. Since the hold margin is larger than the set-up margin, the PLL phase shift can be adjusted to balance the margins. An additional phase shift of 15ps to the existing 90 or 937.5ps phase shift would result in equal margins. This amounts to a total real PLL phase shift of 91 on the echo clock.

Table 3 features the DDR-II SRAM read timing margin analysis at 267MHz when the board trace variations for the Q and CQ/CQn pins are 50ps (approximately 0.3-inch of FR4 trace length variations). A similar timing analysis can be performed for an interface with another FPGA-DDR-II SRAM device combination by replacing timing specifications in Table 3 with those from corresponding data sheets.


Table 3

Design guidelines

The following guidelines are recommended for DDR-II interface implementation:

I/O standard and termination

1.8V or 1.5V HSTL I/O standard with Class I termination is recommended for best performance.

Impedance matching

The recommended value is to a 50-ohm impedance matching. If higher drive strength is needed on the outputs, minimum impedance mode can be used with termination at the far end. This will be adequate for memory interface operation at the highest supported speed for a particular device density and speed grade.

Trace lengths

As described in previous sections, trace lengths for address and control lines should be matched. Likewise, trace lengths for echo clocks and data lines should be closely matched.

Clamshell configuration

DDR-II SRAM pinout supports clamshell configuration, where two DDR-II devices can be placed on either side of the printed circuit board.

Conclusion

DDR-II SRAM devices offer enhanced timing margin and flexibility over prior synchronous SRAMs. Designed for high-bandwidth communications, networking, and DSP applications, DDR-II SRAM devices and Altera's Stratix II, Stratix, and Stratix GX devices help communications system designers take advantage of DDR-II SRAM technology and achieve high memory bandwidth through a simple proven interface.

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