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DFM delays 90 and 65nm, analyst says

Posted: 11 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:international business strategies? dfm? 90nm? wafer? 65nm?

Design for manufacturability (DFM) concerns have slowed the ramp-up of 90nm wafer volumes and will be even more problematic at 65nm, said Handel Jones, CEO of International Business Strategies Inc., at the fabless Semiconductor Association Expo Thursday (Oct. 6).

Jones moderated a panel on DFM in which he presented IBS' latest research. Jones' presentation, along with the panelist comments that followed, provided a warning and a call to action.

Jones noted that 90 and 130nm wafers use the same materials, yet the ramp-up times were under a year and a half for 130nm, and over two years for 90nm. "So why the delay? Our analysis is that leakage is the major factor impacting low yields," Jones said. This includes both sub-threshold and gate-oxide leakage, he noted.

Leakage, according to Jones, is the primary factor in design-related yield loss. And at 90 and 65nm, design-related yield loss is more significant than process-related and reticle-related yield loss, according to IBS data. At 65 nm, design-related yield loss alone may reduce yields by as much as 30 percent, Jones said.

Jones also noted that manufacturing and design costs are taking a larger and larger percentage of total revenues. At 90nm, the manufacturing cost is 60.4 percent of total revenues, while design cost is 11.7 percent. At 65nm, IBS projects that the manufacturing cost will be 69.4 percent of revenues, and the design cost 16.8 percent. "The cost factors are going in the wrong direction," he said.

Jones also cited a very high level of inefficiency in silicon gate utilization. At 90nm, he said, a typical ASIC or ASSP uses around 13 million gates, compared to an available gate count of 30 million gates for a 10mm x 10mm die. Gate utilization isn't expected to be much higher at 65 nm, where 100 million gates will be available.

With costs of $3.5 billion to ramp up to volume production at 65nm, and a time frame of two and a half years, only the largest companies will be able to invest in 65nm fabrication, Jones said. "We're going to an environment where the industry will become increasingly fabless," he said.

Panelists agreed that the challenges for 65nm are huge. "It's never going to be easy again," said Lance Glasser, group vice president for wafer inspection at KLA-Tencor. DFM, he said, must aim at the entire process window rather than "aiming at typical and hoping you hit it."

V.K. Raman, vice president of procurement at Qualcomm, said that high costs require a strong business justification for going to 90 or 65nm. EDA tools are becoming more capable of handling issues like dummy fill, he said, but DFM remains a huge challenge. And if a chip doesn't work, Raman said, "nothing helps us with failure analysis."

DFM must become more design-centric, said Mark Levitt, vice president and general manager for DFM at Cadence Design Systems. "We need smart metal fill during design, not dummy metal fill with post-processing," he said. "We need to deal with full process window variation. Does that mean full statistical timing analysis? The jury is still out on that one."

Anantha Sethuraman, vice president of DFM for Synopsys' silicon engineering group, spoke of chemical metal polishing (CMP) and the need to design circuits that are "polish friendly." He also called for "inspection-aware" dummy metal fill. The key, he said, is manufacturing-aware design.

Defect densities are going up as feature sizes shrink, noted John Kibarian, president and CEO of PDF Solutions. He called for a move from DFM rules to DFM models that can quantify the probability of failure of a circuit element, and allow a tradeoff between yield and performance. He also predicted that it will be necessary to take statistics into account at 45 and 32nm.

Levitt noted that some large companies have been successful at DFM, gaining a competitive advantage. "Will it be democratized so anyone can do DFM?" he asked. "Can we get trusted data into the fabless model? That's what will determine how many people will be successful."

- Richard Goering

EE Times





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