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ARM9 MCU from Atmel draws 2.55A in standby

Posted: 16 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:arm? arm926ej-s core? atmel? at91sam9261? smart arm microcontroller?

Based on the ARM Ltd ARM926EJ-S core, Atmel Corp.s new AT91SAM9261 Smart ARM microcontroller (mcu) consumes only 2.55A in standby mode. The companys newest ARM-based MCU is aimed at wireless handheld applications, such as wireless PoS devices.

Operating at 500Hz, the MCU draws 4005A. Maximum operating power at 180MHz with all peripherals turned on is just 65mA. The processors 200MIPS throughput and its extended instruction set with DSP extensions allow complex DSP functions, such as biometrics, voice recognition, software modems, or encryption/decryption algorithms like RSA, to be executed very quickly in burst mode, so the can system be shut down much of the time. In a typical PoS application with a four-hour battery life, such as a rental car-return processing module, these new MCUs can extend battery life by as much a factor of four to 16 hours, according to Atmel.

Data throughput is significantly increased by the parallelism provided by the multi-layer bus matrix. The bus matrix connects five advanced high-speed bus (AHB) bus masters (processor instruction and data busses, peripheral DMA controller (PDC), and two dedicated DMAs for the USB Host and LCD Controller), to the on-chip peripherals and internal or external memories. Atmel has extended the peripheral DMA control used on its ARM7-based MCUs to include nineteen PDC channels on the AT91SAM9261. The PDC off-loads data transfer operations between the peripheral and memories from the CPU, dramatically increasing data rates and freeing the ARM9 CPU for compute intensive tasks.

This combination of the internal multi-layer AHB bus architecture and the dedicated peripheral DMA controller maximizes processor throughput and optimizes overall system power consumption. For example, the Peripheral DMA controller can facilitate data transfers between the on-chip SRAM and peripherals while the processor simultaneously executes code out of cache or does a cache line fill. Alternatively, the processor can execute code out of on chip SRAM deterministically in parallel to the peripheral DMA controller streaming data from peripherals to external memory.

The AT91SAM9261 has 16KB of data cache, 16KB of instruction/write buffer cache, 160KB of 200MHz, single cycle access SRAM, and 32KB of internal ROM. Atmel has exploited the ARM926EJ-Ss tightly coupled memory (TCM) architecture that allows traditional (non-cache) SRAM to be connected directly to the ARM processor, with no latency. Separate, transparent, easy to use instruction and data caches support WinCE and Linux operating systems, while the TCM SRAM blocks are ideally suited for deterministic real-time operating systems. The on-chip 160KB of SRAM can be partitioned in multiples of 16KB blocks as Instruction TCM, Data TCM, or a buffer for the on-chip peripherals. It gives the programmer maximum flexibility to optimize system performance and power consumption.

The majority of PoS or other data input devices have graphical interfaces that utilize small LCD screens with menus. The AT91SAM9261s on-chip LCD controller supports black-and-white and up to 16M colors, driving active TFT and passive STN LCD displays with a resolution of up to 2,048 x 2,048. The on-chip 160KB of SRAM can be configured as a frame buffer, thereby minimizing the BOM costs associated with an external frame buffer and increasing the battery life.

A USB host controller provides a seamless interface to any USB device, including mouse, keyboard, bar code reader, wireless LAN, DECT or Bluetooth modem. Its dedicated DMA controller and the multi-layer AHB internal bus architecture minimize the processor intervention during data transfers. The USB device port handles connectivity to a PC for system updates and maintenance.

The ARM9 interrupt control scheme is insufficient to meet the demands of interrupt-driven real time systems. Atmel has enhanced this scheme with an 8-level priority, individually maskable, vectored interrupt controller that can handle up to 32 internal or external interrupt sources. Interrupt response time is reduced to a minimum.

The AT91SAM9261 has a system controller with a full complement of supervisory functions including the advanced interrupt controller, timing sources (oscillator and PLLs), real-time periodic interval and watchdog timers, reset and shutdown controllers, backup registers and real-time timer, a power management controller, a debug unit, and PIO controllers that multiplex the I/O lines. The system controller also provides configurable clocks to the processor core and each of the individual peripherals at the appropriate rates. It also sources four programmable output clocks and enables the core and selected peripherals to be placed in idle mode to minimize power consumption.

The AT91SAM9261 peripherals include periodic interval timer, watchdog timer, real time timer, three 32-bit parallel I/O controllers, SD- and Multimedia-compliant Multimedia Card interface (MMC), three synchronous serial controllers, three USARTS, one debug UART, two master/slave serial peripheral interfaces (SPI), a three-channel 16-bit timer/counter, two-wire interface (TWI) and IEEE 1149.1 JTAG Boundary SCAN on all digital pins.

The AT91SAM9261-EK low-cost evaluation kit supports the AT91SAM9261 and its industry-standard ARM architecture gives it compatibility with a wide range of development tools, compilers and debuggers from third-party suppliers.

The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package and is priced at $11.55 in quantities of 10,000 units.

- Marty Gold


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