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DFM tool helps prevent mask failure at 65nm and below

Posted: 12 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:SOLID+? microlithography simulation? image verification? design-for-manufacturing? SIGMA-C Software?

SIGMA-C Software AG, a microlithography simulation company, delivered its first design-for-manufacturing (DFM) productSOLID+, which is a patented microlithography simulation/image verification tool that enables the transfer of electronic designs unto printed wafers to help prevent mask failure at 65nm and below.

According to the press release, this new tool simulate areas up to 200x larger than previously possible with traditional lithography simulation. It identifies hot spots during the chip/cell design process at the resist level for cells larger than 20-by-20?m, letting designers know if their patterns at smaller process nodes can be produced by a photo resist.

"We introduced SOLID+ technology at DAC earlier this year, and now are pleased to provide a proven product that helps companies protect against yield loss by getting things right the first time," said SIGMA-C CEO Peter Feist. "We worked diligently during the last year with technology leaders in the industry to develop our SOLID+ product as a bulletproof way to bridge the gap between design and printed wafer results, and enable silicon accuracy."

Available immediately, SOLID+ is priced from $140,000 and is also available with other SIGMA-C modules such as 3D mask and 3D wafer. The company will demonstrate the SOLID+ product at the Electronic Design and Solution Fair in Yokohama, Japan, later this month.




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