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Engineer readies tool that generates logic specs

Posted: 01 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:richard goering? logic design tool? ldt? combinatorial? sequential logic?

After working in labs designing fault-tolerant flight-control systems, Dave McFarland came to realize that there's no good way to specify logic and look at all the possible combinations. So he built a tool to handle the job.

A graphical aid for developing digital control, McFarland's Logic Design Tool (LDT) generates a complete specification for combinatorial and sequential logic, letting users specify all transitions for all states and all input combinations. It can then provide multiple views of the logic, identify dead or hanging states, search for best- and worst-case performance paths, and generate source files in C, Pascal, Ada, VHDL or Espresso.

"Whenever I look at specs that people have, if there are more than four or five variables, there's a mistake in it," said McFarland, an embedded-software engineer at Lockheed in Atlanta, who previously worked at Boeing and United Technology Corp. His work on LDT, which includes a patent that covers some of the tool's technology, is a separate involvement and McFarland plans to make LDT commercially available through a Website.

Although its heritage is in fault-tolerant flight-control systems, LDT could be useful for anyone working with digital logic, including FPGA and IC designers, McFarland believes. "Wherever there are ones and zeros, this tool can be used," he said. "Everybody is talking about design automation, but nobody can really do it to the point where you can put in a specification at an abstract level, verify that it works according to requirements, press a button and you've got it."

LDT is based on a hierarchy of Karnaugh maps that relate input variables to next-state and output variables. Known "don't care" areas of logic are collapsed. McFarland said LDT offers logic minimization that closely matches the Espresso algorithm.

Many designers start with Karnaugh maps, but these become unwieldy when there are more than a few variables, McFarland said. The solution, he said, is to create some "submaps," take the combinatorial or sequential logic, and divide it up into fields. For a finite state machine, these fields might represent states and inputs. The top level could represent state combinations, while "leaf nodes" represent combinations of input variables.

LDT would be used very early in the design cycle, McFarland said, since it models the behavior of an entire system. It can thus find potential failures well before design implementation. "If you really want to make logic lawyer-proof, you need to specify all transitions for all states for all input combinations," he said.

Asynchronous logic, too
McFarland added that LDT would be a valuable tool for asynchronous logic "because you can specify that you only want transitions between states that are adjacent."

To use LDT, designers use Karnaugh maps or tables to provide information about states and inputs. "If you want to be really rigorous, you can put in one value at a time for each combination," McFarland said. "Or if you're not interested in that, just put in an equation and look at the pattern."

Alternate views include truth tables, if-then-else statements, timing diagrams, Boolean equations, reduction reports and Karnaugh map patterns. The tool does not provide state transition diagrams, which McFarland said are "not rigorous."

State walk-through
An "interactive debugger" in LDT lets users walk through various states in Karnaugh maps and see what happens when inputs change. The tool can also identify dead or hanging states. McFarland is currently adding a capability that can examine state transitions and find best- and worst-case execution times for paths.

Although LDT can output VHDL, it's not compiled at present. McFarland hopes to provide compiled VHDL in the future. As for Verilog, he said, "I'll support anything anybody wants."

- Richard Goering
EE Times




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