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Xilinx upgrades PlanAhead tool

Posted: 09 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:PlanAhead? FPGA? field-programmable gate array? Xilinx?

Xilinx Inc. announced version 8.1 of its PlanAhead software, a hierarchical design and analysis solution for the company's FPGAs. According to the company, the tool allows designers to utilize a hierarchical design methodology that minimizes routing congestion, simplifies clocking and interconnect complexity, and explores implementation options.

Xilinx said that recent customer benchmarks yielded average Fmax performance improvements of 30 percent relative to competing FPGAs, which translates to an average of two speed-grade performance. Complex, multi-clock, high-utilization designs yielded improvements of 56 percent on average over competing solutions.

The software introduces capabilities that aim to streamline the partial reconfiguration design flow, such as additional design rule checking, overlap detection, automatic macro creation for module-to-module IO and a new place-and-route wizard. The product also controls and manages these implementations in the Xilinx ISE software. The company added that these features make partial reconfiguration more accessible for applications, including automotive control functions and software defined radio.

The product's ExploreAhead feature allows users to manage and reuse multiple design strategies. For example, users can create multiple floorplans, each with its own set of options or strategies and process them in a prioritized manner across multiple processes. Other productivity enhancements include improvements to the schematic viewer, design analysis and debug, and a graphical representation of design hierarchy.

The PlanAhead 8.1 design analysis tool is available on several OSes as an option to Xilinx ISE software. Single-user licenses at $5,995 include training.




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