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RFIC and system-design simulators link

Posted: 20 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Janine Love? Xpedion Design Systems? Simulink? MathWorks? RF design?

Xpedion Design Systems Inc. announced an interface to Simulink from The MathWorks to couple system-level and transistor-level simulation for RF design. Designers will be able to use Simulink in conjunction with Xpedion's GoldenGate RFIC simulator to bridge the gap between system-level specifications and transistor-level performance.

"Using Simulink, RF Blockset and Model-Based Design, system engineers can validate an executable model of an entire communications system against requirements," said Colin Warwick, RF product manager at The MathWorks. "With this new link, RFIC designers can reuse that same model as a test environment. This lets users verify that a transistor-level design will behave correctly in the target system."

The current design methodology for advanced RFIC development starts with architectural tradeoffs made in Simulink. Once the specifications are developed, they are passed on to the RF designer, who is responsible to meet those specifications at the transistor level. Through the new design flow, designers can use the actual modulated signal, generated using Simulink, in GoldenGate, thus ensuring specifications are met.

Furthermore, Xpedion is currently developing a co-simulation interface. This interface lets the system-level designer use a live co-simulation link to verify a transistor-level design in GoldenGate by executing a system-level model in Simulink. The benefits include thorough wireless verification and significant time-to-market advantages. This unique flow is available for demonstration upon request.

- Janine Love
eeProductCenter




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