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Sequence addresses needs of SoC designs below 90nm

Posted: 07 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Sequence Design? PowerTheater? SoC? 90nm?

Sequence Design announced the next generation of its PowerTheater design suite to meet the demanding requirements for wireless, mobile and large SoC designs below 90nm.

PowerTheater is the industry standard for low-power design at RTL, with capabilities ranging from early RTL analysis to full-chip power estimates for today's designs. This suite allows users to begin the design process with a firm handle on power budgetsbefore synthesis, when it is too late to optimizeand complete projects with verified results that correlate to silicon. It also allows designers to inspect and probe the precise areas where power is being wasted.

"Below 90nm, power dominates all other issues," said Vic Kulkarni, Sequence president and CEO. "PowerTheater is unique in its ability to analyze and optimize power at RTL, where decisions are made that determine 80 percent of a chip's total power budget, leading to better results and faster time to market."

New PowerTheater features include peak power analysis, power gating, expanded support for RTL and gate-level power estimation of multiple voltage domains, and support for SystemVerilog.

PowerTheater also provides gate-level, time-based power analysis, providing a view of power dissipation as a function of time within a waveform display, and has strong links to CoolTime and other dynamic voltage drop tools for generating state information based on highest activity or highest power.




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