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A designer's guide to CMOS RF models

Posted: 16 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:clyde washburn? integre technologies? RF CMOS design? Serdes? BSIM3 model?

There are three perspectives on RF CMOS design: lower-frequency analog designers moving up their designs to higher frequencies; discrete RF/microwave designers making the transition to the integrated medium; and designers moving digital circuits such as Serdes to the highest frequencies that processes will support. Where it is helpful, we will use these viewpoints to frame the explanations of the difference between RF CMOS and modeling for it.

The substrate
The use of CMOS for traditional digital applications has evolved toward a low-resistivity bulk substrate, with the devices built on a thin, high-resistivity epitaxial (epi) layer. Having the same thickness, the multiple metal interconnect layers preserve flexibility in routing complex digital circuits, thus making all layers equally suitable for routing.

For the low-frequency A/D designer, this is a relatively ideal substrate. But the RF designer would see some negatives. First, parasitic capacitances are maximized by the low resistance of the substrate, and as a result, the transmission lines formed by metal interconnects in the oxide over the substrate have a relatively low characteristic impedance. Secondly, coils built over the substrate are closely coupled to a shorted turnthe substrate itselfthus substantially decreasing both inductance and Q.

An RF CMOS process simply entails giving the entire substrate the high resistivity of the epi layer in a typical digital process. The RF designer now sees something quite differenti.e. the significantly insulating substrate creates a second (small, due to the thick dielectric) capacitor in series with each parasite, functionally shunted by the substrate resistivity.

Parasitic capacitance acquires an additional significant series-resistive component with several positive effects. As coil Qs improve markedly owing to the high resistance of the substrate as a (poor) shorted turn, and substrate currents tend to be inhibited and confined by the significant lateral resistance of the substrate, isolation also improves.

Paralleling metal layers for higher coil Q brings better results. A thicker top metal layer, sometimes with higher conductivity copper in lieu of aluminum, is added to give a big boost to coil Q.

BSIM3 model
Most CMOS designers have encountered the ubiquitous BSIM3 model in its various revisions, such as BSIM3 ver 2. The model was instrumental in the commercial success of CMOS because it had a sensible mix of physics-based and empirical parameters, and was readily adapted to new processes.

The population of the model's parameters is typically accomplished by fabricating devices of various channel widths and lengths, which are then curve-traced at DC to yield the parameters that describe transconductance and resistance. Low-frequency capacitance measurements are then made to populate the capacitive parameters. Typically, an optimizer such as the HSpice Optimizer will be used to refine model parameters to obtain the best fit between actual data and those modeled. When the resulting fit is not as close as desired to the entire range of possible device dimensions, the modeler may decide to "bin"i.e. cause the model to branch out device dimensions to multiple model parameter sets, each optimized for a smaller device size range. This resulting BSIM3 "compact model is well-suited to rapid execution in simulators and for use with P-cells (adjustable size parameter physical layout cells) in layout, giving designers greater flexibility.

It is important to note what is absent in the development of the BSIM3 model. Some device properties were not measured or input to the model. The resistances associated with the gate poly are an important example. Similarly, no high-frequency measurements were made. Thus, the usefulness of the model at high frequencies depends solely on the accuracy as a function of frequency of the equivalent circuit it creates. Fortunately for most purposes, accuracy is enough as the proliferation of commercial CMOS designs proves.

But an RF designer will surely notice that if you simulate a BSIM3 device driven from a sweep frequency source and look at the phase angle of the AC current into the gate relative to the voltage, you will see that it stays at 90 degrees. The device input does not appear significantly resistive at high frequencies as it does in reality due to the series resistance of the polysilicon gate.

How does this manifest itself as a design problem? BSIM3 does not represent the gate resistance as a noise source nor places it in series with the input capacitance to become the parallel input resistance at a given frequency. It is thus impossible to determine optimum RF noise match and make an accurate simulation of RF noise performance with the BSIM3 model. The failure to model the parallel resistive component of input impedance has serious implications for high-speed digital applications like Serdes. The unmodeled, decreasing the parallel resistive input component with frequency, causes significant errors in the gigahertz range for both the frequency domain and delay behavior.

This situation prevailed for many years because the major CMOS foundries' modeling groups had neither the familiarity nor the equipment to evaluate their processes at higher frequencies. Since the BSIM3 model was still very effective for majority of the CMOS designers, the first attempts at improvement proved to be additions outside the BSIM model rather than significant revisions.

The BSIM3 model's fundamental problem was that it ignored physical factors that influence high-frequency operation. Some foundries used the very same BSIM3 model inside an RF sub-circuit, as was used in the digital version of the same process. There is nothing about the way the BSIM3 model is extracted that can cause it to be populated differently for an epi as against a uniform substrate of the same resistivity at the device level.

But at higher frequencies, the appreciable resistance in the drain- and source-diode substrate returns, and in the back-gate return, may not be insignificant. It was thus easy to gain some improvement by enclosing the BSIM3 model in a sub-circuit, which added R and C passives, and sometimes replaced the BSIM3 source- and drain-diode modeling to reflect the substrate change.

The device width per finger is typically fixed to one value or a small number of values at which sub-circuit values have been extracted at common operating points. But this turned out to be a station en route to better RF modeling, since there remained problems, most notable of which was that simulation speeds slowed as the sub-circuits increased component count.

BSIM4 solution
The combined effects of ever-shorter channel devices and increasing frequencies in most designs further highlighted the shortcomings of BSIM3, paving the way for the BSIM4 model. However, the BSIM4 model can be better, but it is not necessarily so.

Traditional methods of populating the model parameters do not include high-frequency correlation and many of the parameters that improve high-frequency accuracy can be either left out or turned off, making the default high-frequency behavior no better than BSIM3. Conversely, if all the capabilities of BSIM4 are used, it can do a good job of matching s-parameter data over all operating conditions at the highest frequencies. BSIM4 models are thus preferable to BSIM3+sub-circuits models if the foundry or service providing the models has correlated them at high frequencies.

Similarly, BSIM4 includes back-gate resistance parameters that improve modeling of back-gate effects if the parameters are correctly populated. While it represents a significant improvement in RF-modeling speed and accuracy, BSIM4 has its own shortcomings. First, it does not include polysilicon gate-depletion effects that alter (increase) the series-equivalent input resistance with decreasing frequency in the 0.1-10GHz range. Secondly, the model is not yet fully symmetrical, meaning it doesn't correctly handle operation in the vicinity of 0Vds, where source and drain interchange. Meanwhile, symmetry is being addressed in BSIM5, which is currently being developed by the BSIM Committee.

It is more important for a designer to have a better understanding of CMOS models than of whether they have the name "RF" attached. A BSIM4 model that is well correlated at RF can be highly accurate from DC to microwave frequencies over all operating conditions, while a more elaborate RF sub-circuit model can be appropriate for only a narrow range of conditions. A designer must find out what type of high frequency correlation is done on the models in the target process, and then consider the implications of what is not done for the design.

- Clyde Washburn
Sr. Scientist
Integre Technologies LLC

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