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SGI adopts Synopsys' topographical tech

Posted: 10 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? Silicon Graphics Inc.? SGI?

Synopsys Inc. announced that Silicon Graphics Inc. (SGI) has deployed Synopsys' Design Compiler topographical technology for its next-generation ASIC designs.

According to the press release, SGI utilized its next-generation NUMAlink testchip as a vehicle to validate the topographical technology for broader deployment within SGI. With its ability to accurately predict post-layout timing and area results in synthesis, topographical technology enables SGI's RTL designers to predict and fix design issues up-front, resulting in significant productivity gains and faster timing closure, said the company.

"We have found the topographical technology to be very effective in delivering predictable flows," noted Gary Benzschawel, design manager at SGI. "Using topographical technology, our RTL designers were able to identify the design issues and fix them prior to physical implementation. The accuracy and predictability of results combined with the advanced optimizations of Design Compiler technology are what our RTL designers need for synthesis at 90nm technology."

Part of Design Compiler Ultra, topographical technology brings accurate timing and area context into the synthesis engine, enabling RTL designers to predict potential design issues early in the design cycle rather than waiting for initial physical implementation results, the company said. It utilizes Synopsys' advanced physical implementation algorithms to eliminate the need for wire-load model-based approximations in synthesis and generates a better starting point for physical design. By providing a better starting point for physical implementation, topographical technology eliminates costly iterations between synthesis and layout to reduce overall design time.




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