Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > T&M
?
?
T&M??

Low-power IC test can be trying

Posted: 16 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Chris Hawkins? Jason Doege? George Kuo? arm? Cadence?

power is at a premium across mainstream applications ranging from battery-powered personal appliances to multiprocessor server farms. For designers, power management means controlling leakage power lost during standby mode and dynamic power consumption when multiple transistors switch in unison to perform desired functions. Designers address increased leakage current at more advanced nanometer technologies through techniques such as multivoltage-supply design, using lower-supply-voltage domains where possible. In turn, design teams must address test issues associated with increased use of non-functional elements such as level-shifter cells.

For control of dynamic power, designers use clock-gating methods to turn off unnecessary registers and minimize the number of transistors that need to switch at any one time. Clock gating can complicate fault isolation and fault observability, and the continued trend toward low-power design promises to heighten this challenge to test. While a typical design might have less than 30 percent of its registers involved in clock gating, 85 percent of all registers can be clock-gated in low-power designs; designers are likely to push this percentage even higher.

At the same time, low-power operation introduces new types of device defects. In particular, complex circuits face increased risk from delay-related failures in low-power modes. Designs that are particularly optimized for low power suffer from lower noise margins due to the combination of increased uncertainty in clocks and lower average slack. As a result, design teams are seeing more multimode timing paths that would pass in higher-voltage modes fail in their low-power operating modes.

Test challenge
For test, the challenges of low-power design extend even further. With their greater susceptibility to delay defects, low-power devices face a greater risk of test escapes, particularly when delay testing is not used or is not optimized. For their part, design teams face a greater challenge to keep power down, particularly as designs scale, the number of nodes increases, voltage decreases and the number of test patterns rises to ensure adequate coverage. Furthermore, during test, devices are operated in a completely different way than during normal usage in their application environment. In many cases, manufacturing test will actually consume more power than system operation.

Consequently, engineers need to be aware of downstream test strategies early in the design process, particularly for low power. A design could be functionally optimized for low power during design, but the result might not be a low-power solution at test.

The objective of low-power design-for-test (DFT) is to optimize test effectiveness, while avoiding the need for expensive high-speed testers to test most low-power test chips. An approach that combines, for example, segmentation of scan chains, for power reduction, with speed-enabling structures (like test-mode applied PLL clocking) can provide a very cost-effective and thorough test solution.


In this increasingly complex environment, EDA capabilities can play a key role in optimizing test well before silicon. Power-aware synthesis methods combined with advanced power-analysis techniques can predict power consumption during test. Moreover, synthesis tools can directly support clock-gating strategies by merging common clock-gating logic, effectively moving gating elements higher in the hierarchy. This approach not only allows fewer gating elements to control larger branches, but also provides a better starting point for clock-tree synthesis. Synthesis tools can further enhance controllability and observability during synthesis, while also checking for DFT violations in clock-gating logic. Synthesis tools add necessary test logic around clock-gating structures to disable gating during scan-shift operation, while still maintaining the testability of the gating logic.

EDA plays a significant role in helping designers identify critical-path sensitivity to multiple operating modes. In the past, design teams needed multiple iterations to find effective test vector sets. For the typical fixed-time delay test, design teams would manually remove multicycle paths to achieve realistic timings and manually adjust vector sets to accommodate tester timings and constraints.

Although this approach was satisfactory when the design featured only a few critical paths, low-power implementations have multiple modes of operation. Indeed, the engineering problem becomes one of identifying the appropriate critical paths at different modes. Newer methods such as true-time delay test achieve higher test effectiveness for designs where clocks affect paths of different length, allowing engineers to perform test generation at more aggressive timings.

Transition-delay ATPG algorithms tend to create tests that use short delay paths. Further, much of the coverage of transition-delay tests come from pseudo-random test data. This creates a problem because traditional delay test methodologies will apply these tests at the target period of the device. Delay defects must then be at least as large as the difference between the length of the short path and the target period to cause a fail.

For example, conventional delay tests might test for defects in a circuit along paths AGHD, BHJE and CJKF, all of which are substantially shorter than the critical path AGHJKF. These traditional tests will be conducted at 5.5ns, so a defect would need to be at least as long as 1.5ns to cause the circuit to fail. However, a delay defect of just about any size smaller than 1.5ns on any segment of AGHJKF will cause the device to fail functionally. This is a major cause of test escapes.

True-time delay test approaches this problem differently. While it still uses efficient ATPG algorithms and pseudo-random data to achieve high coverage in a few patterns, it uses back-annotated timing information (SDF) to guide it in applying them. True-time will also create tests along the same paths previously described, but will apply the test for path CJKF at 2.5ns, AGHD at 3ns and BHJE at 4ns. In this way, very small delay defects can be detected on all segments of path AGHJKF, resulting in a much higher-quality test and far fewer test escapes.

Defect modeling
At the heart of these methods, more effective defect-modeling techniques address the low-power design's unique nature. Conventional test tools have typically worked with stuck-at fault models that fail to represent the situation in multivoltage-domain designs as signals pass from one voltage domain to another. More advanced defect-modeling methods include the pattern fault model, which forms the logical behavior of low-power defects beyond the traditional stuck-at model. Combined with true-time delay tests, pattern fault models allow engineers to examine circuit timing from an SDF file and catch subtle defects that would have evaded detection by traditional logic-based fault methods.

- Chris Hawkins
ARM Inc.

- Jason Doege, George Kuo
Cadence Design Systems Inc.




Article Comments - Low-power IC test can be trying
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top