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Power reduction tool from Azuro extends to 65nm

Posted: 07 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? Azuro? PowerCentric? clock implementation tool? 65nm?

Power-focused EDA startup Azuro Inc. has released version 3 of its PowerCentric low power clock implementation tool, which extends the company's power reduction capabilities to support advanced variability-aware design flows at 65nm and below, Azuro said.

"Clock implementation is becoming increasingly critical at nanometer geometries," said Ashutosh Mauskar, Azuro vice president of product marketing, in a statement. "If performance and gate area are all that matter, then clock implementation is a well contained problem. But if power, routability, and variability are important, then clock implementation becomes a critical part of the design flow."

Mauskar said PowerCentric enables customers to achieve a 15 to 25 percent power reduction without impacting the size of performance of a design.

According to Azuro, PowerCentric operates as a complete replacement for traditional clock tree synthesis in digital ASIC design flows. By unifying clock gate synthesis and clock tree buffering into a single physically-aware optimization engine operating at the placed-gates level in the design flow, PowerCentric is able to insert up to three times more clock gating than current low power industry design flows, the company said.

Key features of the new release include variability-aware low power clock buffering and clock gating; global skew-driven optimization with concurrent multi-corner constraints; automatic useful skew insertion for setup and hold timing closure across multiple modes and corners; clock tree buffering and gating across multiple voltage islands and a GUI with advanced variability-aware clock quality-of-results analysis capabilities, according to Azuro.

- Dylan McGrath
EE Times




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