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Xilinx unveils design tools for 65nm Virtex-5 FPGAs

Posted: 07 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? 8.2I ISE? Integrated Software Environment? Virtex-5 FPGA?

Xilinx Inc. has announced the latest release of its design solution, the 8.2i Integrated Software Environment (ISE) tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs.

Leveraging the high-performance features of the Virtex-5 ExpressFabric technology, the company said the ISE 8.2i design environment enables 30 percent faster performance than previous generation FPGAs. It also promises an integrated timing closure environment and new productivity-enhancing features to fully exploit the performance and power advantages of Virtex-5 devices.

"The ability to meet timing budgets is the number one productivity issue facing designers today. With Virtex FPGAs more often at the heart of complex systems, it is critical that design tools help designers achieve aggressive performance goals while reducing the time spent in the design cycle," said Bruce Talley, VP for design software at Xilinx. "The advanced features and performance of the Virtex-5 family can be quickly and efficiently utilized with ISE 8.2i implementation support, and our new interactive timing closure environment."

Xilinx said the rich feature set of the ISE 8.2i design suite enables designers targeting Virtex-5 devices to meet performance goals with greater certainty and reach design closure in less time.

PerformanceThe company said the new solution builds upon the ISE Fmax technology first introduced with ISE 8.1i to enable the industry's fastest logic performance. The new design suite features next-generation physical synthesis with critical pre- and post-routing optimization for Virtex-5 designs. Enhanced routing support for the new ExpressFabric technology promises reduced levels of logic and signal delay while packing designs more efficiently.

The new solution promises an improved timing closure environment offering tighter correlation between logical and physical design domains. Xilinx said automated cross-probing between constraint entry, timing analysis, floorplanning and implementation reports provides greater visibility and more efficient method for routing and debugging designs. Integration of Xplorer into the 8.2i design flow promises designers the ability to automatically explore various settings and constraints to significantly improve the performance for a given design. ISE 8.2i support for device models and pin assignments and the second generation SparseChevron technology in Virtex-5 FPGAs simplifies PCB design.

In addition, said Xilinx, the new Xpower Estimator tool delivers accurate power estimation based on extensive Virtex-5 device characterization, thus allowing designers to plan for their power budget in advance. Xpower is available as a free download from the company's website.

The ISE 8.2i design suite is accompanied by the release of the ChipScope Pro 8.2 debug and verification software. Available as an add-on option, the ChipScope Pro 8.2 solution promises to reduce verification cycles by up to 50 percent. Also included is the newest release of the ChipScope Pro Serial IO Toolkit, providing simplified debugging of high-speed serial IO designs for Virtex-4 FX FPGAs.

All versions of ISE 8.2i software packages support Windows 2000 and Windows XP and Linux Red Hat Enterprise 3.0. ISE Foundation also supports Solaris 2.8 and 2.9.

ISE 8.2i Foundation and ChipScope Pro 8.2 configurations are immediately available with prices ranging from $695 to $2,495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx website at no charge.




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